Samsung Electronics Co., Ltd.

Tai-Su Park

Si-Young Choi

Yu-Gyun Shin

Dong-Chan Kim

Seong-Hoon Jeong

Jong-Hoon Kang

Jeong-Do Ryu

Jong-Ryeol Yoo

Kyung-won Park

Dong-Gun Park

Jong-Ho Lee

Jung-Woo Park

Gyo-young Jin

U-in Chung

Soo-jin Hong

Won-sang Song

Eui-Joon Yoon

Dong-woon Shin

Sang-Chul Han

Gun-Joong Lee

Mi-jin Kim

Young-Dong Lee

Yoshida Makoto

Jung-Sup Oh

Sung-Jin Kim

Sung-Wook Park

Jae-Man Yoon

Jin-wook Lee

Dong-Ho Ahn

Dong-Kyu Lee

Yu-gyun Shin

Moon-Han Park

Ho-kyu Kang

Ju-Eun Kim

Han-Sin Lee

Jin-Hyuk Choi

Joo-Byoung Yoon

Gyoung-Ho Buh

Sung-tae Ahn

Jung-Soo An

Chang-Woo Ryoo

Jae-Mun Youn

Mi-Young Seo

Ki-Hong Nam

Jung-Geun Park

A method of fabricating a semiconductor device may include: forming a field region defining an active region in a substrate; forming a gate trench in which the active and field regions are partially exposed; forming a gate insulating layer on a surface of the active region; conformally forming a gate barrier layer including metal on the gate insulating layer and partially exposed field region; forming a gate electrode layer including metal on the gate barrier layer; and/or forming a gate capping layer. Forming the gate insulating layer may include forming a first gate oxide layer by primarily oxidizing the active region's surface, and forming a second gate oxide layer between the active region's surface and the first gate oxide layer by secondarily oxidizing the active region's surface. The gate capping layer may be in contact with the gate insulating layer, gate barrier layer, and/or gate electrode layer.

Methods of fabricating gate insulating layers in gate trenches and methods of fabricating semiconductor devices including the same

A recessed channel array transistor may include a substrate, a gate oxide layer, a gate electrode and source/drain regions. The substrate may have an active region and an isolation region. A recess may be formed in the active region. The gate oxide layer may be formed on the recess and the substrate. The gate oxide layer may include a first portion on an intersection between a side end of the recess and a sidewall of the active region and a second portion on a side surface of the recess. The first portion may include a thickness greater than about 70% of a thickness of the second portion. The gate electrode may be formed on the gate oxide layer. The source/drain regions may be formed in the substrate. Thus, the recessed channel array transistor may have a decreased leakage current and an increased on-current.

Recessed channel array transistors, and semiconductor devices including a recessed channel array transistor

Methods of fabricating a semiconductor device include forming a field trench in a silicon substrate, forming a first oxide layer in the field trench, forming a first thinned oxide layer by partially removing a surface of the first oxide layer, and forming a first nitride layer on the first thinned oxide layer.

Methods of fabricating semiconductor device having shallow trench isolation (STI)

A method of fabricating a semiconductor device includes forming a trench in a substrate, forming a pre-gate insulating film along side surfaces and a bottom surface of the trench, and oxidizing the pre-gate insulating film through a densification process.

Method of fabricating semiconductor device

Semiconductor devices, and methods of fabricating the same, include forming device isolation regions in a substrate to define active regions, forming gate trenches in the substrate to expose the active regions and device isolation regions, conformally forming a preliminary gate insulating layer including silicon oxide on the active regions exposed in the grate trenches, nitriding the preliminary gate insulating layer using a radio-frequency bias having a frequency of about 13.56 MHz and power between about 100 W and about 300 W to form a nitrided preliminary gate insulating layer including silicon oxynitride, forming a gate electrode material layer on the nitride preliminary gate insulating layer, partially removing the nitrided preliminary gate insulating layer and the gate electrode material layer to respectively form a gate insulating layer and a gate electrode layer, and forming a gate capping layer on the gate electrode layer to fill the gate trenches.

Semiconductor devices having nitrided gate insulating layer and methods of fabricating the same

In methods of manufacturing a recessed channel array transistor, a recess may be formed in an active region of a substrate. A plasma oxidation process may be performed on the substrate to form a preliminary gate oxide layer on an inner surface of the recess and an upper surface of the substrate. Moistures may be absorbed in a surface of the preliminary gate oxide layer to form a gate oxide layer. A gate electrode may be formed on the gate oxide layer to fill up the recess. Source/drain regions may be formed in an upper surface of the substrate at both sides of the gate electrode. Thus, the oxide layer may have a uniform thickness distribution and a dense structure.

Methods of forming recessed channel array transistors and methods of manufacturing semiconductor devices

Methods of forming integrated circuit devices include forming an electrically conductive layer containing silicon on a substrate and forming a mask pattern on the electrically conductive layer. The electrically conductive layer is selectively etched to define a first sidewall thereon, using the mask pattern as an etching mask. The first sidewall of the electrically conductive layer may be exposed to a nitrogen plasma to thereby form a first silicon nitride layer on the first sidewall. The electrically conductive layer is then selectively etched again to expose a second sidewall thereon that is free of the first silicon nitride layer. The mask pattern may be used again as an etching mask during this second step of selectively etching the electrically conductive layer.

Methods of forming integrated circuit devices having electrically conductive layers therein with partially nitridated sidewalls

A fin field effect transistor includes a fin protruding from a semiconductor substrate, a gate insulating layer formed so as to cover upper and lateral surfaces of the fin, and a gate electrode formed across the fin so as to cover the gate insulating layer. An upper edge of the fin is rounded so that an electric field concentratedly applied to the upper edge of the fin through the gate electrode is dispersed. A thickness of a portion of the gate insulating layer formed on an upper surface of the fin is greater than a thickness of a portion of the gate insulating layer formed on a lateral surface of the fin, in order to reduce an electric field applied through the gate electrode.

Fin field effect transistor and method of fabricating the same

A semiconductor device is manufactured by forming trenches in a substrate and selectively performing Plasma Ion Immersion Implantation and Deposition (PIIID) on a subset of the trenches in the substrate. The PIIID may be performed on only a portion of a surface of at least one of the trenches in the substrate. Semiconductor devices can include a semiconductor substrate having first, second and third trenches therein, and an oxide liner layer that fully lines the first trenches, that does not line the second trenches and that partially lines the third trenches.

Methods of manufacturing trench isolation structures using selective plasma ion immersion implantation and deposition (PIIID)

Methods of manufacturing a semiconductor device, which can reduce hot electron induced punchthrough (HEIP) and/or improve the operating characteristics of the device include selectively forming an oxynitride layer in a device isolation layer according to the characteristics of transistors isolated by the device isolation layer. The methods include forming first trenches and second trenches on a substrate, forming an oxide layer on the surfaces of the first trenches and the second trenches, selectively forming an oxynitride layer on the second trenches by using plasma ion immersion implantation (PIII), and forming a buried insulating layer in the first trenches and the second trenches. The buried insulating layer may be planarized to form a first device isolation layer in the first trenches and a second device isolation layer in the second trenches.

Methods of manufacturing semiconductor devices

A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The method may also include forming a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, forming a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and forming a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction.

Methods of fabricating vertical channel field effect transistors having insulating layers thereon

A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second source gas. The first source gas includes n-type or p-type impurity elements, and the second source gas includes a dilution element regardless of the electrical characteristic of a doped region.

Methods of forming semiconductor device

Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor includes forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.

Double gate field effect transistor and method of manufacturing the same

A field effect transistor can include a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The transistor can also include a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction. Related methods are also disclosed.

Vertical channel field effect transistors having insulating layers thereon

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Seoul, South Korea

Tai-Su Park