Novatek Microelectronics Corp.

Tai-Hung Lin

Chang-Tien Tsai

Wen-Ching Huang

Jung-Fu Hsu

Chiao-Ling Huang

Jhih-Siou Cheng

Jr-Ching Lin

Teng-Jui Yu

Chun-Yu Liao

Hong-Dyi Chang

A chip on film package is disclosed, including a flexible film and a chip. The flexible film includes a film base, a patterned metal layer includes a plurality of pads and disposed on an upper surface of the film base, and a dummy metal layer covering a lower surface of the film base and capable of dissipating heat of the chip. The dummy metal layer comprises at least one opening exposing the second surface, and at least one of the plurality of pads is located within the at least one opening in a bottom view of the chip on film package. The chip is mounted on the plurality of pads of the patterned metal layer.

Chip on film package

A chip on film package includes a base film, a patterned circuit layer, a chip and a reinforcing sheet. The base film includes a first surface, a second surface opposite to the first surface and a mounting region located on the first surface. The patterned circuit layer is disposed on the first surface. The chip is mounted on the mounting region and electrically connected to the patterned circuit layer. The reinforcing sheet is disposed on the first surface and/or the second surface and exposes the chip, wherein a flexibility of the reinforcing sheet is substantially equal to or greater than a flexibility of the base film.

Chip on film package with reinforcing sheet and manufacturing method of chip on film package with reinforcing sheet

A quad flat no-lead (QFN) package structure including a lead frame, a semiconductor die, and an encapsulating material. The lead frame includes a die pad and a plurality of contacts surrounding the die pad. The semiconductor die is disposed on the die pad and electrically connected to the plurality of contacts, wherein a shortest distance between the semiconductor die and a first side of the die pad is shorter than a shortest distance between the semiconductor die to a second side of the die pad, and the first side is opposite to the second side. The encapsulating material encapsulates the lead frame and the semiconductor die and partially exposing the plurality of contacts, wherein an aspect ratio of the QFN package is substantially equal to or greater than 3.

Quad flat no-lead package structure

Chip on film package with reinforcing sheet

A chip on film package includes a base film, a chip and a heat-dissipation structure. The base film includes a first surface and a second surface opposite to the first surface. The chip is disposed on the first surface and has a chip length along a first axis of the chip and a chip width along a second axis of the chip perpendicular to the first axis. The heat-dissipation structure includes a covering portion. The covering portion at least partially covers the chip, exposes a side surface of the chip, and has a first length along the first axis and a second length along the second axis being longer than the chip width of the chip. The side surface connects a top surface and a bottom surface of the chip. A heat-dissipation structure is also provided.

Chip on film package and heat-dissipation structure for a chip package

A chip on film package includes a base film, a chip and a heat-dissipation sheet. The base film includes a first surface. The chip is disposed on the first surface and having a chip length along a first axis of the chip. The heat-dissipation sheet includes a covering portion and a first extending portion connected to the covering portion and attached to first surface. The covering portion at least partially covers the chip and having a first length along the first axis. The first extending portion has a second length along the first axis substantially longer than the first length of the covering portion, and the covering portion exposes a side surface of the chip, wherein the side surface connects a top surface and a bottom surface of the chip.

An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure, a first internal bonding wire, and a second internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The third bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the third bonding pad structure via the first internal bonding wire. The third bonding pad structure is electrically coupled to the second bonding pad structure via the second internal bonding wire.

Integrated circuit device

An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, and an internal bonding wire is provided. The first bonding pad structure is disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The second bonding pad structure is disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor substrate. The first bonding pad structure is electrically coupled to the second bonding pad structure via the internal bonding wire. The integrated circuit device having a better electrical performance is provided by eliminating internal resistance drop in power supply trails or ground trails, and improving signal integrity of the integrated circuit device.

An IC chip package and a chip-on-glass structure using the same are provided. The IC chip package includes an IC chip having a circuit surface, and plural copper (Cu) bumps formed on the circuit surface. Moreover, a non-conductive film (NCF) could be formed on the circuit surface to cover the Cu bumps. The chip-on-glass structure includes a glass substrate, plural electrodes such as aluminum (Al) electrodes formed on the glass substrate, and a conductive film formed on the electrodes. The conductive film contains a number of conductive particles. When the IC chip package is coupled to the glass substrate, the Cu bumps can be coupled to the corresponding electrodes via conductive particles.

IC chip package and chip-on-glass structure using the same

An integrated circuit device including a substrate, a first internal bonding pad, a second internal bonding pad, an external bonding pad and a bonding wire is provided. A first circuit and a second circuit are embedded in the substrate. The first internal bonding pad is disposed on a surface of the substrate and electrically coupled to the first circuit. The second internal bonding pad is disposed on the surface of the substrate and electrically coupled to the second circuit. The second internal bonding pad is electrically coupled to the first internal bonding pad via the bonding wire. The external bonding pad is electrically coupled to the first internal bonding pad.

An integrated circuit device including a substrate, a first internal bonding pad, a second internal bonding pad, an external bonding pad and a bonding wire is provided. A first circuit, a second circuit, at least one interconnect line and an electrostatic discharge protection circuit are embedded in the substrate. The first internal bonding pad is disposed on a surface of the substrate and electrically connected to the first circuit. The second internal bonding pad is disposed on the surface of the substrate and electrically connected to the second circuit. The first internal bonding pad is electrically connected to the second internal bonding pad via the bonding wire. The first internal bonding pad is electrically connected to the electrostatic discharge protection circuit via the interconnect line. The electrostatic discharge protection circuit is electrically connected to the external bonding pad which is used for electrically connecting an external package lead.

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Hsinchu, Taiwan

Tai-Hung Lin