Intel Corporation

Sony Group Corporation

Tahoe Research, Ltd.

Daedalus Prime LLC

Sony Corporation

Intel Corporatiion

Tahir Ghani

Anand S Murthy

Jack T Kavalieros

Gilbert W Dewey

Glenn A Glass

Biswajeet Guha

Willy Rachmady

Matthew V Metz

Abhishek A Sharma

Van H Le

Harold W Kennel

Stephen M Cea

Oleg Golonzka

Leonard P Guler

Seung Hoon Sung

Rishabh Mehandru

Sean T Ma

Benjamin Chu-Kung

Mark T Bohr

Mauro J Kobrinsky

Michael L Hattendorf

Cheng-Ying Huang

Kelin J Kuhn

Seiyon Kim

Swaminathan Sivakumar

Bernhard Sell

Rafael Rios

Charles Henry Wallace

Brian S Doyle

Mark L Doczy

Kaan Oguz

Kevin O'Brien

Chia-Hong Jan

Aaron D Lilak

Patrick R Morrow

Sanaz Kabehie Gardner

Robert S Chau

Ravi Pillarisetty

Dmitri E Nikonov

Marko Radosavljevic

Niloy Mukherjee

Prashant Majhi

Kevin Lai Lin

Christopher J Jezewski

Uygar E Avci

Brian Joseph Greene

Charles C Kuo

Seongjun Park

Sasikanth Manipatruni

Ian A Young

Elijah V Karpov

Chandra S Mohapatra

William Hsu

Shriram Shivaraman

Karthik Jambunathan

Joseph M Steigerwald

Yih Wang

Abhijit Jayant Pethe

Christopher P Auth

Cory C Bomberger

Mark Armstrong

Szuya S Liao

Annalisa Cappellani

Roza Kotlyar

Pei-Hua Wang

Nazila Haratipour

Nadia M Rahhal-Orabi

Chieh-Jen Ku

Christopher J Wiegand

Travis W LaJoie

Wilfred Gomes

Byron Ho

Kinyip Phoa

Subhash M Joshi

Jack Hwang

Jason W Klaus

Alan M Myers

Cory E Weber

Steven J Keating

Daniel Bourne Aubertine

Ashish Agrawal

Mark Y Liu

Fatih Hamzaoglu

Rajesh Kumar

Tristan A Tronic

Kevin J Lee

Robert G James

Martin D Giles

Mohit K Haran

Elliot Tan

Miriam Ruth Reshotko

Andrew W Yeoh

Nick Lindert

Markus Kuhn

Kevin Fischer

Doug B Ingerly

Ebrahim Andideh

Huang-Lin Chao

Ruth Amy Brain

Satyarth Suri

Contact over active gate (COAG) structures with uniform and conformal gate insulating cap layers, and methods of fabricating contact over active gate (COAG) structures using uniform and conformal gate insulating cap layers, are described. In an example, an integrated circuit structure includes a gate structure. An epitaxial source or drain structure is laterally spaced apart from the gate structure. A dielectric spacer is laterally between the gate structure and the epitaxial source or drain structure, the dielectric spacer having an uppermost surface below an uppermost surface of the gate structure. A gate insulating cap layer is on the uppermost surface of the gate structure and along upper portions of sides of the gate structure, the gate insulating cap layer distinct from the dielectric spacer.

Contact over active gate structures with uniform and conformal gate insulating cap layers for advanced integrated circuit structure fabrication

IC devices including angled transistors formed based on angled wafers are disclosed. An example IC device includes a substrate and a semiconductor structure. A crystal direction of a crystal structure in the semiconductor structure is not aligned with a corresponding crystal direction (e.g., having same Miller indices) of a crystal structure in the substrate. An angle between the two crystal directions may be 4-60 degrees. The semiconductor structure is formed based on another substrate (e.g., a wafer) that has a different orientation from the substrate, e.g., flats or notches of the two substrates are not aligned. The crystal direction of the semiconductor structure may be determined based on a crystal direction in the another substrate. The semiconductor structure may be a portion of a transistor, e.g., the channel region and S/D regions of the transistor. The semiconductor structure may be angled with respect to an edge of the substrate.

Integrated circuit devices with angled transistors formed based on angled wafers

Integrated circuit structures having recessed self-aligned deep boundary vias are described. For example, an integrated circuit structure includes a plurality of gate lines. A plurality of trench contacts extends over a plurality of source or drain structures, individual ones of the plurality of trench contacts alternating with individual ones of the plurality of gate lines. A backside metal routing layer is extending beneath one or more of the plurality of gate lines and beneath one or more of the plurality of trench contacts. A conductive structure couples the backside metal routing layer to one of the one or more of the plurality of trench contacts. The conductive structure includes a pillar portion in contact with the one of the one or more of the plurality of trench contacts, the pillar portion on a line portion, the line portion in contact with and extending along the backside metal routing layer.

Integrated circuit structure with recessed self-aligned deep boundary via

A structure includes a first vertical stack of horizontal nanowires having a first width. A second vertical stack of horizontal nanowires is spaced apart from and parallel with the first vertical stack of horizontal nanowires and has the first width. A first gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, a second gate structure portion over the second vertical stack of horizontal nanowires, and a gate cut between the first gate structure portion and the second gate structure portion. A third vertical stack of horizontal nanowires has a second width greater than the first width. A fourth vertical stack of horizontal nanowires is spaced apart from and parallel with the third vertical stack of horizontal nanowires and has the second width. A second gate structure is continuous over the third vertical stack of horizontal nanowires and over the fourth vertical stack of horizontal nanowires.

Integrated circuit structures having maximized channel sizing

Structures having ultra-high conductivity global routing are described. In an example, an integrated circuit structure includes a device layer having a plurality of transistors. A plurality of metallization layers is above the plurality of transistors of the device layer. One or more of the metal layers includes a material having a critical temperature greater than 10 Kelvin and less than 300 Kelvin.

Integrated circuit structures having ultra-high conductivity global routing

Fin cuts in neighboring gate and source or drain regions for advanced integrated circuit structure fabrication is described. For example, an integrated circuit structure includes a horizontal stack of semiconductor nanowire portions. A dielectric gate spacer is vertically over the horizontal stack of semiconductor nanowire portions. A gate isolation structure is laterally adjacent to a first side of the horizontal stack of semiconductor nanowire portions. A source or drain isolation structure is laterally adjacent to a second side of the horizontal stack of semiconductor nanowire portions.

Fin cut in neighboring gate and source or drain regions for advanced integrated circuit structure fabrication

Techniques are provided herein to form semiconductor devices having gate cut structures. Adjacent semiconductor devices having semiconductor regions (e.g., fins or nanoribbons) extending in a first direction have a gate structure that extends over the semiconductor regions in a second direction and are separated by a gate cut structure extending in the first direction and interrupting the gate structure. The gate cut structure further extends between adjacent source or drain regions (corresponding to the adjacent semiconductor devices). A dielectric liner on at least a sidewall and/or top surface of the source or drain regions and also extends up a sidewall surface of the gate cut structure. In some cases, the gate structure includes a gate dielectric present on the semiconductor regions, but not present on the gate cut structure. A contact may pass through the liner and at least partially land on a source or drain region.

Gate cut structures

Techniques are provided herein to form semiconductor devices having different pitches, yet maintaining a substantially similar depth to the diffusion regions between the semiconductor regions. In an example, a row of semiconductor devices having semiconductor regions extending in a first direction can include some devices having a diffusion region with a first width in the first direction and some devices having a diffusion region with a second width in the first direction, where the second width is different from the first width. The depths of the diffusion regions having both the first and second widths may be substantially similar (e.g., within 2 nm or less of one another). In some examples, the bottom surface of at least one of the wider diffusion regions has a step profile.

Deep etch processing for transistors having varying pitch

Source and drain contacts that provide improved contact resistance and contact interface stability for transistors employing silicon and germanium source and drain materials, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such source and drain contacts include a contact layer of co-deposited titanium and silicon on the silicon and germanium source and drain. The disclosed source and drain contacts improve transistor performance including switching speed and reliability.

Co-deposition of titanium and silicon for improved silicon germanium source and drain contacts

Embodiments herein describe techniques for a semiconductor device including a substrate. A first capacitor includes a first top plate and a first bottom plate above the substrate. The first top plate is coupled to a first metal electrode within an inter-level dielectric (ILD) layer to access the first capacitor. A second capacitor includes a second top plate and a second bottom plate, where the second top plate is coupled to a second metal electrode within the ILD layer to access the second capacitor. The second metal electrode is disjoint from the first metal electrode. The first capacitor is accessed through the first metal electrode without accessing the second capacitor through the second metal electrode. Other embodiments may be described and/or claimed.

Capacitor connections in dielectric layers

Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

Fin cut and fin trim isolation for advanced integrated circuit structure fabrication

Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.

Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability

Fin trim plug structures for imparting channel stress are described. In an example, an integrated circuit structure includes a fin including silicon, the fin having a top and sidewalls. The fin has a trench separating a first fin portion and a second fin portion. A first gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the first fin portion. A second gate structure including a gate electrode is over the top of and laterally adjacent to the sidewalls of the second fin portion. An isolation structure is in the trench of the fin, the isolation structure between the first gate structure and the second gate structure. The isolation structure includes a first dielectric material laterally surrounding a recessed second dielectric material distinct from the first dielectric material, the recessed second dielectric material laterally surrounding an oxidation catalyst layer.

Method of fabricating integrated circuits with fin trim plug structures having an oxidation catalyst layer surrounded by a recessed dielectric material

A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.

Wrap-around trench contact structure and methods of fabrication

Integrated circuit structures having backside gate tie-down are described. In an example, a structure includes a first vertical stack of horizontal nanowires over a first sub-fin, and a second vertical stack of horizontal nanowires over a second sub-fin, the second vertical stack of horizontal nanowires spaced apart from and parallel with the first vertical stack of horizontal nanowires. A gate structure includes a first gate structure portion over the first vertical stack of horizontal nanowires, wherein the first gate structure extends along an entirety of the first sub-fin. A second gate structure portion is over the second vertical stack of horizontal nanowires, wherein the second gate structure does not extend along an entirety of the second sub-fin. A gate cut is between the first gate structure portion and the second gate structure portion.

Integrated circuit structures having backside gate tie-down

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Portland, OR, United States of America

Tahir Ghani