Spin Memory, Inc.

Integrated Silicon Solution, (cayman) Inc.

TaeJin Pyon

Neal Berger

Kuk-Hwan Kim

Susmita Karmakar

Benjamin S Louie

A memory device for storing data comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. The memory device also comprises a cache memory operable for storing a second plurality of data words, wherein further each data word of the second plurality of data words is either awaiting write verification or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments of the memory bank, wherein each primary segment of the plurality of primary segments of the cache memory is sub-divided into a plurality of secondary segments, and each of the plurality of secondary segments comprises at least one counter for tracking a number of valid entries stored therein.

Error cache system with coarse and fine segments for power optimization

A memory device comprises a memory bank comprising a plurality of addressable memory cells, wherein the memory bank is divided into a plurality of segments. Further, the device comprises a cache memory operable for storing a second plurality of data words, wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. The cache memory is divided into a plurality of primary segments, wherein each primary segment of the cache memory is direct mapped to a corresponding segment of the plurality of segments, wherein each primary segment is sub-divided into a plurality of secondary segments, and wherein each of the plurality of secondary segments comprises at least one counter for tracking a number of entries stored therein.

Heuristics for selecting subsegments for entry in and entry out operations in an error cache system with coarse and fine grain segments

A method of writing data into a memory device is disclosed. The method comprises utilizing a pipeline to process write operations of a first plurality of data words addressed to a memory bank. The method further comprises writing a second plurality of data words into an error buffer associated with the memory bank wherein each data word of the second plurality of data words is either awaiting write verification associated with the memory bank or is to be re-written into the memory bank. Additionally, the method comprises monitoring an occupancy level of the error buffer and determining if the occupancy level of the error buffer has increased beyond a predetermined threshold. Subsequently, responsive to a determination that the occupancy level of the error buffer has increased beyond the predetermined threshold, increasing a write voltage of the memory bank, wherein subsequent write operations are performed at a higher write voltage.

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Fremont, CA, United States of America

TaeJin Pyon