Apple Inc.

Taegui Kim

Yifan Kao

Jun Chung Hsu

Jun Zhai

Chih-Ming Chung

Young Doo Jeon

Yikang Deng

An asymmetric stackup structure for an SoC package substrate is disclosed. The package substrate may include a substrate with one or more insulating material layers. A first recess may be formed in an upper surface of the substrate. The recess may be formed down to a conductive layer in the substrate. An integrated passive device may be positioned in the recess. A plurality of build-up layers may be formed on top of the substrate. At least one via path may be formed through the build-up layers and the substrate to connect contacts on the lower surface of the substrate to contacts on the upper surface of the build-up layers.

Asymmetric Stackup Structure for SoC package substrates

Semiconductor packaging substrates and processing sequences are described. In an embodiment, a packaging substrate includes a build-up structure, and a patterned metal contact layer partially embedded within the build-up structure and protruding from the build-up structure. The patterned metal contact layer may include an array of surface mount (SMT) metal bumps in a chip mount area, a metal dam structure or combination thereof.

Semiconductor packaging substrate fine pitch metal bump and reinforcement structures

Asymmetric stackup structure for SoC package substrates

Growing community of inventors

San Jose, CA, United States of America

Taegui Kim