Samsung Electronics Co., Ltd.

Tae-Sung Yoon

Jin-Ho Kim

Young-hee Song

Hee-Jin Park

Sang-Young Kim

Byung-seo Kim

Min-Young Son

Hyeon Deuk Hwang

Pyoung-Wan Kim

Cheol-Joon Yoo

Chan-Suk Lee

Mu-Seob Shin

A wiring substrate for a semiconductor chip includes a substrate, first and second wiring layers and a plurality of first and second bonding pads. The substrate has a first surface and a second surface opposite to the first surface, a window extending from the first surface to the second surface to expose chip pads of a semiconductor chip adherable to the first surface. The first and second wiring layers of a multi-layered structure are sequentially formed on the second surface of the substrate with at least one insulation layer interposed between the first and second wiring layers. A plurality of the first and second bonding pads are respectively connected to the first and second wiring layers, the first and second bonding pads having a concavo-convex arrangement on the second surface of the substrate along a side of the window.

Wiring substrate for a semiconductor chip, and semiconducotor package having the wiring substrate

Provided are a semiconductor package, a method of forming the semiconductor package, and a printed circuit board (PCB). The semiconductor package includes: a PCB including at least two parts divided by an isolation region; a semiconductor chip mounted on the PCB; and a molding layer disposed in the isolation region. The method includes: preparing a PCB, the PCB including a plurality of chip regions and a scribe region; forming isolation regions dividing each of the chip regions into two parts, the isolation regions including inner isolation regions and outer isolation regions, the inner isolation regions being provided in the chip regions, the outer isolation regions being provided at both ends of the inner isolation regions so as to extend toward the scribe region; mounting semiconductor chips on the chip regions; and cutting the PCB along the scribe region to divide the chip regions into at least two parts.

Semiconductor package and method of forming the same, and printed circuit board

The stack package may have a structure in which unit packages may be inserted into slots of a receiving substrate. The unit package may have a plurality of connecting pads. The receiving substrate may have substrate pads, which may be electrically connected to the connecting pads of the unit packages inserted in the slots by mechanical contact. The slots may be provided at regular vertical intervals so that the unit packages may be stacked in the vertical direction. A semiconductor module may include stack packages installed on at least one surface of a module substrate.

Stack package and semiconductor module implementing the same

Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while the appearance cracks and the warpage defects can be prevented.

Stacked semiconductor package having fan-out structure through wire bonding

A semiconductor package and a package mounting substrate can be joined using a conductive material column. Each of the semiconductor package and the package mounting substrate include an insulating protective opening exposing a wiring layer therein. The solder column resides within the insulating protective openings to electrically couple the wiring layers. The insulating protective openings protect the solder column against stress faults to form reliable electrical connections and to support high-density electrical connections between the semiconductor package and the package mounting substrate.

Structure for joining a semiconductor package to a substrate using a solder column

Provided are a method of manufacturing wafer-level chip-size packages and a molding apparatus suitable for practicing the method whereby a semiconductor wafer having a plurality of semiconductor chips formed thereon may be encapsulated. The semiconductor wafer, typically with a plurality of conductive bumps extending from the semiconductor chips, will be placed in a cavity formed between upper and lower molds. Injection molding of an encapsulant composition or compression molding of encapsulant sheets may then be used to apply encapsulating layers to the upper and lower surfaces of the semiconductor wafer in a substantially simultaneous manner, thereby reducing the likelihood of warping and mechanical damage to the semiconductor wafer. The wafer-level chip-size packages can then be separated from the encapsulated semiconductor wafer.

Method of manufacturing wafer-level chip-size package and molding apparatus used in the method

In example embodiments of the present invention, a structure of a BGA semiconductor chip package includes a substrate having first and second surfaces, a semiconductor chip having a plurality of bonding pads, and mounted on the first surface of the substrate, and plurality of in/out (I/O) solder balls and dummy solder balls provided on the second surface of the substrate, wherein the I/O solder balls are electrically connected to the semiconductor chip and the dummy solder balls are electrically isolated from the semiconductor chip, and the I/O solder balls and the dummy solder balls have the same ball size and ball pitch and are uniformly provided over the second surface of the substrate.

BGA semiconductor chip package and mounting structure thereof

Semiconductor package accomplishing fan-out structure through wire bonding

A method for manufacturing semiconductor devices is provided in which an organic adhesive layer is formed on the backside of a semiconductor wafer after being thinned by a backlapping process and cured to form a B-stage adhesive layer. Using the B-stage adhesive layer, the semiconductor device may then be attached to a circuit substrate and then subjected to additional curing to form a C-stage adhesive layer. Such semiconductor devices may also be attached directly to a lower semiconductor chip or, in the alternative, may be attached to a spacer mounted that is or will be mounted on a lower semiconductor chip or the circuit substrate. The organic adhesive is selected to counteract stresses induced by a passivation layer formed on the active surface, thereby reducing or preventing warping of the semiconductor wafer and eliminating the need for a separate resin paste adhesive during the chip attaching process.

Growing community of inventors

Cheonan-si, South Korea

Tae-Sung Yoon