Samsung Electronics Co., Ltd.

Tae-ryong Kim

Young-woo Lee

Tae-Hoon Kim

Byung-chul Kim

Jong-Heui Song

Dong-yun Kim

Jae-pil Kim

Do-hyeong Kim

Ka-soon Yim

Jae-hee Hwang

Hag-pil Kim

Dai-sick Moon

Hee-su Park

Chung-Howan Kim

Jong-sik Won

Kwang-jin Jung

Byeung-wook Choi

Kwang-Jin Jung

Chung-howan Kim

Ho Ko

A thermoelectric-cooling temperature control apparatus for a semiconductor device fabrication facility maintains a temperature condition, such as the temperature of a wafer, stable during the fabrication process. The apparatus includes a heat exchanger having a thermoelectric cooling element which produces a Peltier Effect to cause the element to absorb and radiate heat according to current flowing through the element

Thermoelectric-cooling temperature control apparatus for semiconductor device fabrication facility

A photoresist mask removing method for effectively removing polymers produced as by-products during etching of a metal layer includes processing the polymers prior to removal to facilitate removal thereof. To remove the photoresist mask remaining on a semiconductor substrate after the metal layer is dry-etched in an etching chamber, the semiconductor substrate is preferably conveyed from the etching chamber to an ashing chamber without vacuum break. The semiconductor substrate is pretreated by supplying N,gas into the ashing chamber under the vacuum state without applying RF power to the ashing chamber to blow the N,gas on the semiconductor substrate heated up to a predetermined temperature. This pretreatment modifies the polymer by-products to facilitate removal thereof during ashing. The photoresist mask and the polymer by-products are removed by ashing in the ashing chamber.

Method for removing photoresist mask used for etching of metal layer and other etching by-products

A multiple reaction chamber system includes a transfer chamber, a load lock chamber connected to the transfer chamber, and a plurality of reaction chambers connected to the transfer chamber. An alignment chamber is connected to the transfer chamber, disposed along a path of wafer transfer from the load lock chamber to the plurality of reaction chambers, and includes a wafer aligner. A wafer recognition, disposed along a post-aligner portion of the path of wafer transfer system, recognizes an identification code of an individual wafer. A controlling system is in data communication with the wafer recognition system for selecting a selected chamber of the plurality of reaction chambers into which the individual wafer is to be transferred. Because individual wafers can be associated with each reaction chamber, a defective reaction chamber can be identified immediately and its use discontinued so that unproductive operations can be eliminated.

Multiple reaction chamber system having wafer recognition system and method for processing wafer using same

A method of manufacturing semiconductor device that improves the alignment margin between a contact hole and a device pattern includes a layer having an upper vertically shaped portion and a lower symmetrically inclined shaped portion. That is, the lower portion is tapered.

Method of manufacturing semiconductor devices and semiconductor device capacitor manufactured thereby

A method of forming a low-k dielectric insulating layer includes forming the dielectric insulating layer and then removing hydrogen bonds in the dielectric insulating layer. The dielectric layer as formed is preferably a HSQ film which contains the structure Si--O--H. Hydrogen is removed from the dielectric layer by either: a heat treatment in plasma, an ozone reduction process, an ion implantation process, or electron beam bombardment.

Method of making intermetal dielectric layers having a low dielectric

A dry etching apparatus used for manufacture of a semiconductor device includes a plasma confinement ring secured by screws to a cathode, an anode, and a metal focusing ring extending around the anode for enhancing the uniformity of the plasma. The screws are located a maximum distance away from the focusing ring. Thus, micro-arcing is prevented from occurring between the focusing ring and the screws. The confinement ring is also designed to distribute the plasma stream only onto the wafer, so that the generation of contamination particles is suppressed during etching.

Dry etching apparatus having means for preventing micro-arcing

A semiconductor device includes a metal wiring layer having a plurality of parallel, actual metal lines, with an endmost one of the actual metal lines being disposed adjacent a wiring-free region. The actual metal lines are electrically connected to an active circuit portion of the semiconductor device. At least one dummy metal line is interposed between the endmost one of the actual metal lines and the wiring-free region, with the at least one dummy metal line being disconnected from the active circuit portion. The dummy metal line(s) serve to prevent corrosion of the actual metal lines when the metal wiring layer is patterned by an etching process.

Semiconductor device having a corrosion-resistant metal wiring layer

Growing community of inventors

Suwon, South Korea

Tae-ryong Kim