Stats Chippac Pte. Ltd.

Tae Keun Lee

Hun Teak Lee

Hyung Jun Jeon

Soo Jung Park

Sangkwon Lee

Sung Soo Kim

SeongMin Lee

Youngnam Choi

Kyungsic Yu

Youngcheol Kim

Young Chan Ko

SooMoon Park

DaeWook Yang

YoRim Lee

Hye Ran Lee

Jaepil Kim

JungHo Seo

Taeho Kim

Minseok Kim

An integrated circuit package system includes: providing a substrate; forming a conductive layer over the substrate; forming a mold gate layer having an organic material without polymerization over the conductive layer; and attaching an integrated circuit over the substrate adjacent the mold gate layer.

Integrated circuit package system with mold gate

A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.

Stackable integrated circuit package system

A method of manufacture of an integrated circuit package system includes forming a substrate with a device thereover, forming an encapsulation having a planar top surface to cover the device and the substrate spanning to an extraction side of the encapsulation, and forming a recess in the encapsulation from the planar top surface.

Integrated circuit package system and method of manufacture thereof

A semiconductor package system includes providing a substrate having a plurality of thermal vias extending through the substrate. A solder mask is positioned over the plurality of thermal vias. A plurality of thermally conductive bumps is formed on at least some of the plurality of thermal vias using the solder mask. An integrated circuit die is attached to the plurality of thermally conductive bumps. An encapsulant encapsulates the integrated circuit die.

Semiconductor package system with thermal die bonding

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming layers having non-horizontal strip patterns and non-vertical strip patterns over the substrate; mounting an integrated circuit device on the substrate adjacent the non-horizontal strip patterns and the non-vertical strip patterns; and applying an encapsulation over the integrated circuit device, the encapsulation restricted by the layers to prevent the encapsulation from reaching an edge of the substrate.

Integrated circuit packaging system with encapsulant containment and method of manufacture thereof

A semiconductor wafer scale package system is provided including providing a semiconductor substrate having a through-hole via with a conductive coating, forming a filled via by filling the through-hole via with a conductive material, coupling a package substrate to the filled via, and singulating a chip scale package from the semiconductor substrate and the package substrate.

Semiconductor wafer scale package system

An integrated circuit package system is provided including providing a substrate having a die attached and electrically bonded thereto. The system includes forming heat slug pillars on the substrate, positioning a heat slug on the heat slug pillars, and encapsulating the substrate, the die, the heat slug pillars, and the heat slug in a mold compound. The system includes singulating the substrate, the die, the heat slug, and the mold compound.

Integrated circuit package system with heat slug

An integrated circuit package system is provided forming a substrate having an integrated circuit die thereon, thermally connecting a heat slug and a resilient thermal structure to the integrated circuit die, and encapsulating the resilient thermal structure.

Integrated circuit package system with a heat sink

An integrated circuit package system includes a substrate having an integrated circuit die thereon; a heat slug having a tie bar, the tie bar having characteristics of singulation from an adjacent heat slug; and an encapsulant molded on the substrate, the heat slug, and the integrated circuit die includes the encapsulant which fills all of the space between the integrated circuit die and the heat slug.

Integrated circuit package system using heat slug

An integrated circuit package system includes providing a substrate having an integrated circuit die thereon. A support is provided on the substrate. A heat slug having a tie bar is positioned by the tie bar on the support. The substrate and the integrated circuit die are encapsulated with an encapsulant, the encapsulant in contact with the heat slug. The substrate, heat slug, and encapsulant are singulated to remove the support.

An integrated circuit package system that includes: providing an electrical interconnect system including a first lead-finger system and a second lead-finger system; stacking a second device over a first device between the first lead-finger system and the second lead-finger system; connecting the second device to the second lead-finger system with a bump bond; stacking a dummy device over the second device; and connecting the first device to the first lead-finger system with a wire bond.

Integrated circuit package system employing thin profile techniques

An integrated circuit package system is provided including forming a substrate with a device thereover, forming an encapsulation having a planar top surface to cover the device and the substrate spanning to an extraction side of the encapsulation, and forming a recess in the encapsulation from the planar top surface.

Integrated circuit package system

An integrated circuit package system includes: providing a package carrier; forming a first channel in the package carrier; mounting a first integrated circuit device over the package carrier and adjacent to the first channel; mounting a second integrated circuit device over the package carrier and adjacent to the first channel; and forming a contiguous underfill fillet with the first channel and under both the first integrated circuit device and the second integrated circuit device.

Growing community of inventors

Ichon-si, South Korea

Tae Keun Lee