Samsung Electronics Co., Ltd.

Other

Smasung Electronics Co., Ltd.

Tae-Je Cho

Un-Byoung Kang

Sun-kyoung Seo

Cha-Jea Jo

In-Young Lee

Hyung-Sun Jang

Hyuek-Jae Lee

Jung-Hwan Kim

Heung-Kyu Kwon

Yun-seok Choi

Seung-Kwan Ryu

Yun-Hyeok Im

Ji-hwang Kim

Min-Ha Kim

Ho-jin Lee

Hyunsoo Chung

Tae-Hong Min

Ho-Geon Song

Se-Young Jeong

Dong-hyeon Jang

Min-Seung Yoon

Woon-Seong Kwon

Jong-Yeon Kim

Cha-jea Jo

Gun-ho Chang

Yong-hwan Kwon

Tae-Hun Kim

Hyun-Soo Chung

Kyol Park

Se-yong Oh

Byung-Hyug Roh

Jongyeon Kim

Choong-bin Yim

Eun-Mi Kim

Tae-hyeong Kim

Ji-sun Hong

Byoung-Soo Kwak

Yeong-Kwon Ko

Jong-Yun Myung

Jin-Woo Park

Min-Soo Kim

Yong-Hwan Kwon

Ju-Il Choi

Sang-Uk Han

Kyu-Dong Jung

Dong-min Kim

Sang-Sick Park

Sang-wook Park

Kwang-Chul Choi

Won-keun Kim

Jong-bo Shim

Seungduk Baek

Chung-Sun Lee

Seok-hyun Lee

Hyung-gil Baek

Sung-Yong Park

Yung-cheol Kong

Jung-Seok Ahn

Byeong-yeon Cho

Byoung-rim Seo

Young-kun Jee

Myeong-soon Park

Young-Kun Jee

Jong-Kook Kim

Hyeok-Man Kwon

Keum-hee Ma

Sang-Wook Ji

Hyoung-Yol Mun

Yong-won Choi

Ji-woong Park

Dong-Gil Lee

Beoung-ouk Min

Kyung-wook Paik

Yeong-Iyeol Park

Yeong-kwon Ko

Young-Bok Kim

Jong-Bo Shim

Sang-Cheon Park

Ji-won Shin

A semiconductor package includes: a plurality of unit redistribution layers vertically stacked, each including: a first polymer layer having a first via hole pattern; a second polymer layer formed on the first polymer layer, and having a redistribution pattern on the first polymer layer and a second via hole pattern in the first via hole pattern; a seed layer covering sidewalls and bottom surfaces of the redistribution pattern and the second via hole pattern; a conductive via plug formed in the second via hole pattern; and a conductive redistribution line formed in the redistribution pattern; a connection terminal disposed on a bottom surface of a lowermost unit redistribution layer and electrically connected to the conductive via plug; a semiconductor device mounted on the unit redistribution layers with a conductive terminal interposed therebetween. Upper surfaces of the second polymer layer, the conductive redistribution line and the conductive via plug are substantially coplanar.

Interposer, semiconductor package, and method of fabricating interposer

A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat. According to the method, no undercut occurs under a conductive structure and there are no bubbles between adjacent conductive structures, thus device reliability is enhanced and pattern accuracy is realized.

Method of fabricating an interposer

The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.

Semiconductor chip, semiconductor package including the same, and method of manufacturing semiconductor chip

A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.

Semiconductor package

In one embodiment, a semiconductor device includes a semiconductor substrate having a first surface, and a second surface opposite to the first surface. The second surface defines a redistribution trench. The substrate has a via hole extending therethrough. The semiconductor device also includes a through via disposed in the via hole. The through via may include a via hole insulating layer, a barrier layer, sequentially formed on an inner wall of the via hole. The through via may further include a conductive connector adjacent the barrier layer. The semiconductor device additionally includes an insulation layer pattern formed on the second surface of the substrate. The insulation layer pattern defines an opening that exposes a region of a top surface of the through via. The semiconductor devices includes a redistribution layer disposed in the trench and electrically connected to the through via. The insulation layer pattern overlaps a region of the conductive connector.

Semiconductor device, fabricating method thereof and semiconductor package including the semiconductor device

A method of manufacturing a semiconductor package includes: providing a package substrate having a first surface and a second surface opposite the first surface; providing a first semiconductor chip on the package substrate, the first semiconductor chip having a first surface facing the second surface of the package substrate, a second surface opposite the first surface of the first semiconductor chip, and lateral surfaces extending from the first surface of the first semiconductor chip to the second surface of the first semiconductor chip; providing a molding layer covering the lateral surfaces of the first semiconductor chip and covering the second surface of the package substrate; and providing a plurality of through-molding conductive vias outside the lateral surfaces of the first semiconductor chip. The through-molding conductive vias may be formed before forming the molding layer and may pass through the molding layer. The through-molding conductive vias may extend beyond a first surface of the molding layer.

Semiconductor chip package and method of manufacturing the same

A chip-stacked semiconductor package includes a first chip having a first front surface, a first back surface, and a first connection member on the first front surface, the first back surface being opposite to the first front surface; a second chip having a second front surface, a second back surface, a second connection member and a first through-silicon via (TSV) electrically connected to the second connection member, the second back surface opposite to the second front surface, and the second connection member on the second front face; and a first sealing member between the first front surface and the second front surface, the first sealing member filling a space between the first connection member and the second connection member, the first connection member of the first chip and the second connection member of the second chip being symmetric with respect to each other.

Chip-stacked semiconductor package and method of manufacturing the same

A semiconductor package includes a package member and a stress controlling layer. The package member includes an encapsulation layer and at least one chip. The encapsulation layer encapsulates the at least one chip. The stress controlling layer is disposed on a surface of the package member. The stress controlling layer has an internal stress to the extent that the stress controlling layer prevents the package member from having warpage.

Semiconductor package and manufacturing method thereof

Semiconductor devices and methods for manufacturing a semiconductor device include a first semiconductor substrate in which a first scribe line region and a first chip region are defined, a first alignment mark inside the first semiconductor substrate and in the first scribe line region so as to be spaced apart from an upper side of the first semiconductor substrate, a second semiconductor substrate on the first semiconductor substrate and in which a second scribe line region and a second chip region are defined, and a second alignment mark inside the second semiconductor substrate and in the second scribe line region so as to be spaced apart from an upper side of the second semiconductor substrate, wherein the second semiconductor substrate is on the first semiconductor substrate so that positions of the first alignment mark and the second alignment mark correspond to each other.

Alignment mark for semiconductor device

Provided are an initiator and a method for debonding a wafer supporting system. The initiator for debonding a wafer supporting system includes a rotation chuck having an upper surface on which a wafer supporting system (WSS), which includes a carrier wafer, a device wafer, and a glue layer for bonding the carrier wafer and the device wafer to each other, is seated to rotate the wafer supporting system, a detecting module detecting a height and a thickness of the glue layer and a laser module generating a fracture portion on the glue layer through irradiating a side surface of the glue layer with a laser on the basis of the height and the thickness of the glue layer.

Initiator and method for debonding wafer supporting system

Provided are semiconductor packages having through electrodes and methods of fabricating the same. The method may include may include forming a wafer-level package including first semiconductor chips stacked on a second semiconductor chip, forming a chip-level package including fourth semiconductor chips stacked on a third semiconductor chip stacking a plurality of the chip-level packages on a back surface of the second semiconductor substrate of the wafer-level package, polishing the first mold layer of the wafer-level package and the first semiconductor chips to expose a first through electrodes of the first semiconductor chip, and forming outer electrodes on the polished first semiconductor chips to be connected to the first through electrodes, respectively.

Semiconductor packages having through electrodes and methods of fabricating the same

An electronic device is provided, which includes a substrate having an electrically conductive contact pad thereon and an electrically conductive connection terminal on the contact pad. The connection terminal includes an electrically conductive pillar structure and a solder layer that extends on the pillar structure and contacts a protruding portion of a sidewall of the pillar structure. The pillar structure can include a lower pillar layer, a diffusion barrier layer on the lower pillar layer and an upper pillar layer on the diffusion barrier layer. In some additional embodiments of the invention, the protruding portion of the sidewall of the pillar structure includes an outermost portion of an upper surface of the diffusion barrier layer. This can be achieved by making a width of the diffusion barrier layer greater than a width of the upper pillar layer when viewed in transverse cross-section.

Semiconductor devices with solder-based connection terminals and method of forming the same

Methods of fabricating semiconductor packages are provided. One of the methods includes forming a protection layer including metal on a first surface of a substrate to cover a semiconductor device disposed on the first surface of the substrate, attaching a support substrate to the protection layer by using an adhesive member, processing a second surface of the substrate opposite to the protection layer to remove a part of the substrate, and detaching the support substrate from the substrate.

Pre-package and methods of manufacturing semiconductor package and electronic device using the same

A method of manufacturing a semiconductor package includes forming a bonding layer on a carrier substrate, bonding an inner substrate to the carrier substrate, removing the carrier substrate, and forming a gap-filling portion by removing a portion of the bonding layer to expose a portion of a solder ball provided in the inner substrate. The inner substrate may be mounted on a package substrate and a semiconductor chip may be mounted on the inner substrate.

Method of fabricating a packaged integrated circuit with through-silicon via an inner substrate

Growing community of inventors

Yongin-si, South Korea

Tae-Je Cho