Hyundai Electronics Industries Co. Ltd.

Tae Hum Yang

Joo Young Kim

Soon Won Hong

Jong Seuk Lee

Chae Hyun Jung

Young Dong Joo

Jong Bae Jeong

Il Hyun Choi

Mun Pyo Hong

The present invention discloses a mask set for compensating for a misalignment between the patterns and method of compensating for a misalignment between the patterns. A mask set of the present invention comprises a first mask consisted of a mask substrate on which a main pattern and a plurality of sub-patterns are formed, said sub-patterns formed at a side of the main pattern; a second mask consisted of a mask substrate on which a plurality of hole patterns are formed, the hole patterns corresponded to spaces between the main pattern and the sub-patterns of the first mask, respectively when the first and second mask are overlapped to each other; and a third mask consisted of mask substrate on which a plurality of bar patterns are formed, the bar patterns corresponded to the hole patterns of the second mask, respectively when the second and third mask are overlapped to each other.

Mask set for compensating a misalignment between patterns and method of compensating a misalignment between patterns using the same

Mask set for compensating a misalignment between patterns

A voltage control circuit according to the present invention comprises a charge pump for generating a voltage depending on the clock signal inputted thereto; an oscillator for determining the cycle of the clock signal inputted to the charge pump; an adjusting unit for detecting the voltage generated from the charge pump to output an adjusting signal so that the oscillator can vary the cycle of the clock signal inputted to the charge pump.

Voltage control circuit

A voltage generation circuit of a semiconductor memory device has a charge pump circuit for supplying a voltage required to operate the semiconductor memory device; a voltage divide circuit having a plurality of capacitors and connected to the output of the charge pump circuit to divide the output of the charge pump circuit; an initialization means for discharging charges charged to the plurality of capacitors according to a reset signal; and a differential amplifier for controlling the charge pump circuit according to the result of comparison of the voltage divide circuit and a reference voltage.

Semiconductor memory device having a multi-step pulse generation circuit

The present invention discloses a flash memory device, a first well and second well are formed in a substrate, a plurality of memory cell are formed in the second well and arranged in an array having a multiplicity of bit lines and word lines. Voltage is applied to the first well and second well, respectively, with time interval so that an over erasing of the memory cell and lowering of cycling characteristic can be prevented.

Erasing circuit for a flash memory device having a triple well structure

The present invention provides a method for programming and erasing a plurality of flash memory cells simultaneously while the power consumptions for those operations are significantly reduced, and the method for programming a memory cell of a flash memory device, wherein the memory cell is formed on a P-well surrounded by an N-well of a semiconductor substrate, including the steps of: applying a negative voltage to a control gate of the memory cell; applying a positive voltage to a drain of the memory cell; applying a positive voltage to the P-well, wherein the voltage is the same as or lower than the voltage applied to the drain; applying a power supply voltage to the N-well; and leaving a source of the memory cell uncoupled, wherein the steps are performed either in sequence or at random.

Growing community of inventors

Seoul, South Korea

Tae Hum Yang