International Business Machines Corporation

Intel Corporation

Lenovo (singapore) Pte. Ltd.

Tae Hong Kim

Moises Cases

Rohan U Mandrekar

Bhyrav M Mutnury

Nusrat I Sherali

Michael Jay Shapiro

Jinwoo Choi

Nanju Na

Mahesh Bohra

Kevin Bills

Sang Y Lee

Edmund Juris Sprogis

Michael F McAllister

Sergio Clavijo

Donghwi Kim

Nam Huu Pham

Paul Marian Harvey

James S Dinh

Nickolaus J Gruendler

Shyamkumar Thoziyoor

A reconfigurable coupled inductor is disclosed. In one embodiment, the reconfigurable coupled inductor comprises metal rings and switches coupled to the metal rings to control at least one inductor property (e.g., coupling coefficient) based on a closed (e.g., on) or open state (e.g., off) of each switch.

Reconfigurable coupled inductor

An apparatus and methods for reducing overshoot and undershoot using a reconfigurable inductor in a switching voltage regulator. Specifically, the switching voltage regulator includes a reconfigurable inductor, the reconfigurable inductor has a conductive control ring, and the conductive control ring has an adjustable enclosed area controlled by at least a first switch, wherein the reconfigurable inductor has a varying inductance based on a state of at least the first switch and the adjustable enclosed area of the conductive control ring is shown.

Method and apparatus for reducing overshoot and undershoot using a reconfigurable inductor for switching mode voltage

A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.

Coreless multi-layer circuit substrate with minimized pad capacitance

Example multi-layer printed circuit boards ('PCBs') are described as well as methods of manufacturing a PCB. Embodiments include depositing upon layers of laminate printed circuit traces and joining the layers of laminate. Embodiments also include drilling at least one via hole through the layers of laminate and placing in the via hole a via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a second metal having a conductivity lower than the conductivity of copper.

Through-hole-vias in multi-layer printed circuit boards

Corles multi-layer circuit substrate with minimized pad capacitance

Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.

Minimizing plating stub reflections in a chip package using capacitance

A capacitor in a semiconductor substrate employs a conductive through-substrate via (TSV) as an inner electrode and a columnar doped semiconductor region as an outer electrode. The capacitor provides a large decoupling capacitance in a small area, and does not impact circuit density or a Si3D structural design. Additional conductive TSV's can be provided in the semiconductor substrate to provide electrical connection for power supplies and signal transmission therethrough. The capacitor has a lower inductance than a conventional array of capacitors having comparable capacitance, thereby enabling reduction of high frequency noise in the power supply system of stacked semiconductor chips.

Integrated decoupling capacitor employing conductive through-substrate vias

Example multi-layer printed circuit boards ('PCBs') are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.

One or more decoupling capacitors are coupled to a low inductance mount that is connected to the bottom layer of a printed circuit board (PCB) on which a semiconductor module is mounted. The low inductance mount includes a magnetic planar structure with vias that are coupled to the one or more decoupling capacitors and to like vias positioned on the PCB.

Noise suppressor for semiconductor packages

Plating stub resonance in a circuit board may be mitigated by increasing surface roughness of the plating stub conductor. Roughening the plating stub increases its resistance due to the skin effect at higher frequencies, which decreases the quality factor of the transmission line and consequently increases the damping factor, to reduce any resonance that would occur in the plating stub as formed prior to roughening. The surface roughness can be increased in a variety of ways, including chemical processes, by selectively applying a laser beam, or by applying an etch-resistance material in selected locations.

Mitigation of plating stub resonance by controlling surface roughness

A method, system or computer usable program product for performing timing analysis on an array circuit including receiving in memory a set of pins to be timed, selecting with a data processor a cross section of the array circuit including the set of pins wherein a backtrace is performed from the set of pins to identify a set of bus groups, each bus group having a plurality of timing pins, and assigning timing for an assigned pin of a first bus group equal to timing calculated for a surrogate pin of the first bus group based on array circuit regularity.

Timing analysis of an array circuit cross section

A system for providing power and ground vias for power distributions systems includes first and second conductive layers on a microelectronic package. The conductive layers may include one or more conductive components such as, but not limited to, power planes, ground planes, pads, traces, and the like for electrically connecting to electronic components. A via may electrically connect the first and second conductive layers. The via may have a cross-section of at least three partially-overlapping shapes. Each of the shapes partially overlaps at least two of the other shapes. The shapes may be, for example, circular, triangular, rectangular, square, polygonal, rhomboidal shape, or any other shape.

Growing community of inventors

Austin, TX, United States of America

Tae Hong Kim