Amkor Technology, Inc.

Tae Heon Lee

Mu Hwan Seo

Young Suk Chung

Jung Woo Lee

Jae Jin Lee

Jae Hak Yee

Hyung Ju Lee

Sung Sik Jang

Ku Sun Hong

A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in electrical communication with the bond pads. The semiconductor chip, the chip paddle and the leads are encapsulated by an encapsulation material. The height of the semiconductor package of the invention is minimized by half etching the chip paddle to reduce the thickness of the chip paddle such that the thickness of the chip paddle is less than the thickness of the leads. Preferably, the chip paddle of the present invention is about 25-75% of the thickness of the leads.

Semiconductor package having reduced thickness

A semiconductor package is disclosed that comprises a chip paddle and a semiconductor chip that has a plurality of bond pads. The semiconductor chip is located on an upper surface of the chip paddle. Leads are formed at intervals along the perimeter of the chip paddle. The leads are in electrical communication with the bond pads. The semiconductor chip, the chip paddle and the leads are encapsulated by an encapsulation material. The height of the semiconductor package of the invention is minimized by half etching the chip paddle to reduce the thickness of the chip paddle such that the thickness of the chip paddle is less than the thickness of the leads. Preferably, the chip paddle of the present invention is about 25&#x2013;75% of the thickness of the leads.

A semiconductor leadframe and a semiconductor package using same. More particularly, a semiconductor leadframe offering improved solder joint strength between a semiconductor package and a motherboard is disclosed. The leadframe comprises a plate-type frame body; a chip paddle on which a semiconductor chip may be mounted; a plurality of internal leads located radially and spaced at regular intervals about the perimeter of the chip paddle; external leads extending outward from the internal leads and with their terminals connecting to the frame body; and dam bars at the juncture of each external and internal lead for additional support and to ensure that the external leads remain exposed during subsequent encapsulation processes. The leadframe of the present invention providing additional solder joint strength through the use of internal leads having different lengths or surface areas.

Leadframe and semiconductor package with improved solder joint strength

Disclosed is a semiconductor package and a method for manufacturing the same. A planar or substantially planar die pad is disposed within a leadframe and is connected to the leadframe by a plurality of tie bars. An perimeter of an upper and lower surface of the die pad is half-etched to increase the moisture-permeation path of the finished package. A plurality of rectangular leads extends from the leadframe toward the die pad without contacting the die pad. A silver-plating layer may be formed on the upper surface of the leadframe. A semiconductor chip is mounted on the upper surface of the die pad in the leadframe. After deflashing, the package is treated with a sulfuric (H SO )-based solution to restore the internal leads to their original color. Prior to singulation, the externally exposed bottom surfaces of the leads are plated with copper, gold, solder, tin, nickel, palladium, or an alloy thereof to form a predetermined thickness of a plating layer. The singulation step comprises forming a burr at a peripheral side surface of the leads in the upward direction. The finished package may be marked with a recognition mark to enable a user to more easily identify the first lead.

Semiconductor device having increased moisture path and increased solder joint strength

A method for making a packaged semiconductor having improved defect testing and increased production yield. The method includes providing a plurality of unit leadframes in a matrix, wherein each of the leadframes comprises a die pad connected to the leadframes by a plurality of tie bars, a plurality of tabs extending from each of the unit leadframes towards the respective die pad without contacting the die pad, and a plurality of dam bars provided on a boundary of the tabs. Next a semiconductor chip having a plurality of bond pads is mounted to a first surface of the die pad in each of said unit leadframes via an adhesive. The bond wires between each of the plurality of die pads are electrically connected to the respective semiconductor chip in each of the plurality of unit leadframes. Each of the unit leadframes is then encapsulated with an encapsulant. Each of the unit semiconductor packages is singulated from the matrix by cutting said dam bars between the tabs in each of the unit leadframes on two X-axes simultaneously, while leaving a connection between the tie bars and the unit leadframes intact. Then, each of the unit semiconductor packages are cut at the dam bars between the tabs on two Y-axes simultaneously, while leaving a connection between the tie bars and the unit leadframes intact. The entire matrix is next tested. Finally, the tie bars in each unit semiconductor package is cut to separate the semiconductor packages from the matrix.

Growing community of inventors

Kuri-shi, South Korea

Tae Heon Lee