Samsung Electronics Co., Ltd.

Tae-hee Choe

Hwa-sung Rhee

Nae-in Lee

Sang-Su Kim

Geum-Jong Bae

Geum-jong Bae

Sang-su Kim

Kyung-wook Lee

Jung-Woo Park

Young-Gun Ko

Won-sang Song

Gil-gwang Lee

CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A SiGelayer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The SiGelayer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peak Ge concentration level is greater than x=0.15 and the concentration of Ge in the SiGelayer varies from the peak level to a level less than about x=0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the SiGelayer varies from the peak level where 0.2&#x3c;x&#x3c;0.4 to a level where x=0 at the first junction. The SiGelayer also has a retrograded arsenic doping profile therein relative to the surface. This retrograded profile may result in the SiGelayer having a greater concentration of first conductivity type dopants therein relative to the concentration of first conductivity type dopants in a channel region within the unstrained silicon active layer. The total amount of dopants in the channel region and underlying SiGelayer can also be carefully controlled to achieve a desired threshold voltage.

CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and method of forming same

Methods of forming CMOS integrated circuit devices and substrates having buried silicon germanium layers therein

The present invention provides a semiconductor transistor using an L-shaped spacer. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.

Semiconductor transistor using L-shaped spacer

CMOS integrated circuit devices and substrates having buried silicon germanium layers therein and methods of forming same

A method of fabricating a SOI substrate includes sequentially forming a first semiconductor layer, which may be either a porous semiconductor layer or a bubble layer, a second semiconductor layer and a buried oxide layer on a front surface of a semiconductor substrate, forming an etch stopping layer, which may be a silicon nitride layer, on a front surface of a supporting substrate; contacting the etch stopping layer with the buried oxide layer to bond the semiconductor substrate to the supporting substrate; and selectively removing the semiconductor substrate and the first semiconductor layer to expose the second semiconductor layer. The method may additionally include forming a buffer oxide layer between the supporting substrate and the etch stopping layer.

Method of fabricating SOI substrate having an etch stop layer, and method of fabricating SOI integrated circuit using the same

Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure. These methods may comprise the steps of: providing a integrated circuit substrate having surface and a gate on the integrated circuit substrate; subsequently removing portions of the integrated circuit substrate to form a pair of recessed regions below the surface of the integrated circuit substrate, the recessed region being defined by a floor and sidewall in the integrated circuit substrate; and epitaxially growing a layer on the floor and sidewall of each recessed region.

Methods for fabricating field effect transistors having elevated source/drain regions

A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern. In the state that the silicon germanium layer is selectively removed, a gate insulation layer is formed to cover the exposed surface of the active layer pattern. A gate conductivity layer is stacked on the substrate by a chemical vapor deposition (CVD) to fill the gate region including the cavity. The middle part of the channel region of the active layer pattern can be patterned to be divided by multiple patterns that are formed in a line.

Semiconductor device having gate all around type transistor and method of forming the same

In a CMOS semiconductor device having a substrate, a gate insulating layer formed on the substrate, at least one first polysilicon gate formed over the substrate in at least one PMOS transistor region, and at least one second polysilicon gate formed over the substrate in at least one NMOS transistor region, a total amount of Ge in the first polysilicon gate is the same as that in the second polysilicon gate, a distribution of Ge concentration in the first and/or second polysilicon gate is different according to a distance from the gate insulating layer, and Ge concentration in a portion of the first polysilicon gate adjacent to the gate insulating layer is higher than that in the second polysilicon gate. The Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than two times as high as that in the second polysilicon gate. For example, it is preferable that the Ge concentration in the portion of the first polysilicon gate adjacent to the gate insulating layer is more than 20%, and Ge concentration in a portion of the second polysilicon gate adjacent to the gate insulating layer is below 10%.

CMOS semiconductor device and method of manufacturing the same

The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas. A method of fabricating the semiconductor transistor includes a process, where the high- and medium-concentration junction areas are formed simultaneously by the same ion-implantation step and the substrate is annealed before forming the low-concentration junction area.

Semiconductor transistor using L-shaped spacer and method of fabricating the same

A SOI substrate having an etch stopping layer, a SOI integrated circuit fabricated on the SOI substrate, and a method of fabricating both are provided. The SOI substrate includes a supporting substrate, an etch stopping layer staked on the supporting substrate, a buried oxide layer and a semiconductor layer sequentially stacked on the etch stopping layer. The etch stopping layer preferably has an etch selectivity with respect to the buried oxide layer. A device isolation layer is preferably formed to define active regions. The device isolation, buried oxide and etch-stop layers are selectively removed to form first and second holes exposing the supporting substrate without damaging it. Semiconductor epitaxial layers grown on the exposed supporting substrate therefore have single crystalline structures without crystalline defects. Thus, when impurity regions are formed at surfaces of the epitaxial layers, a high performance PN diode having a superior leakage current characteristic may be formed.

SOI substrate having an etch stop layer and an SOI integrated circuit fabricated thereon

CMOS integrated circuit devices include an electrically insulating layer and an unstrained silicon active layer on the electrically insulating layer. An insulated gate electrode is also provided on a surface of the unstrained silicon active layer. A Si Ge layer is also disposed between the electrically insulating layer and the unstrained silicon active layer. The Si Ge layer forms a first junction with the unstrained silicon active layer and has a graded concentration of Ge therein that decreases monotonically in a first direction extending from a peak level towards the surface of the unstrained silicon active layer. The peal Ge concentration level is greater than x&equals;0.15 and the concentration of Ge in the Si Ge layer varies from the peak level to a level less than about x&equals;0.1 at the first junction. The concentration of Ge at the first junction may be abrupt. More preferably, the concentration of Ge in the Si Ge layer varies from the peak level where 0.2<x<0.4 to a level where x&equals;0 at the first junction. The Si Ge layer also has a retrograded arsenic doping profile therein relative to the surface.

CMOS integrated circuit devices and substrates having unstrained silicon active layers

Field effect transistors (FETs) include an integrated circuit substrate having a surface, and a gate on the surface. A pair of recessed regions in the substrate are located beneath the surface. Respective ones of the recessed regions are located on respective opposite sides of the gate. Each of the recessed regions define a sidewall and a floor. An elevated source/drain structure on each of the recessed regions is at least as thick adjacent to the gate as remote from the gate. A gate spacer may be included between the gate and the elevated source/drain region. The gate spacer can comprise an insulating film. Preferably, the source/drain structure extends to the sidewall of the recessed region. The elevated source/drain structure is preferably free of a facet adjacent the gate. The present invention also relates to methods for fabricating a field effect transistors (FET) having an elevated source/drain structure. These methods may comprise the steps of: providing a integrated circuit substrate having a surface and a gate on the integrated circuit substrate; subsequently removing portions of the integrated circuit substrate to form a pair of recessed regions below the surface of the integrated circuit substrate, the recessed region being defined by a floor and sidewall in the integrated circuit substrate; and epitaxially growing a layer on the floor and sidewall of each recessed region.

Field effect transistors having elevated source/drain regions

Method of manufacturing CMOS semiconductor device

In an SOI-type semiconductor device and a method of forming the same a semiconductor device is formed in an SOI-type substrate that is composed of a lower silicon layer, a buried oxide layer, and an SOI layer. The SOI substrate includes a device region isolated by a device isolation layer and the buried oxide layer, in which a source/drain region for forming at least one MOSFET at a body composed of the SOI layer is formed; and a ground region which is isolated from the device region by the device isolation layer and is composed of the body. A bottom portion of the device isolation layer is separated from the buried oxide layer by a connecting portion that electrically connects a body of the device region to a body of the ground region through the SOI layer. A silicon germanium layer is formed in the SOI layer, and at least partially remains at the SOI layer connecting the body of the device region to the body of the ground region in the connecting portion. Preferably, the device isolation layer is a trench-type isolation layer. The silicon germanium layer is formed at an interface between the SOI layer and the lowest portion of the SOI layer, i.e., a buried oxide layer, or is sandwiched between silicon layers that constitute the SOI layer under the SOI layer.

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Seoul, South Korea

Tae-hee Choe