Tokyo Shibaura Denki Kabushiki Kaisha

Kabushiki Kaisha Toshiba

Tokyo Shibaura Electric Co., Ltd.

Tadashi Shibata

Kei Kurosawa

Nozomu Harada

Kiyoshi Urui

Yasuo Ikawa

Misao Miyata

Masahiko Kawamura

Noboru Amano

A semiconductor device has a semiconductor substrate, a source and a drain region, each formed at the surface of said semiconductor substrate, and each having a potential barrier with respect to the semiconductor substrate. A gate electrode is formed on the semiconductor substrate and positioned between the source and drain regions. The gate electrode controls the height of discrete energy levels of carriers of said semiconductor substrate, and provides a conduction state and a non-conduction state depending upon the existence or non-existence of resonant tunneling current flow.

Semiconductor devices

A concave portion having a V-shaped cross section is formed in a contact region of a p-type silicon substrate. The contact region is defined by a hole formed in an insulative layer formed over the substrate. An n-type diffusion layer is formed in the substrate so as to surround the concave portion. The n-type diffusion layer is connected to a drain region of a FET. A metal layer is formed on the insulative layer such that the metal layer is in electric contact with the diffusion layer through the increased surface area of the concave portion in the contact region.

Semiconductor device and manufacturing method thereof

Semiconductor device MOSFET with V-shaped drain contact

A method for manufacturing a semiconductor device of the invention comprises the steps of

Method for manufacturing a semiconductor device utilizing self-aligned

A programmable semiconductor integrated circuit device is disclosed, which includes different kinds of MSI scale function blocks formed on a substrate. First wiring lines extending in a row direction are connected to input terminals of the function blocks, respectively. Second wiring lines are connected to output terminals of the function blocks, respectively. The second wirings are T-shaped and have respective line components extending in a column direction, with the first wiring lines. Floating gate type field effect transistors are provided, in a matrix manner, at mutually electrically insulated crossing points among the first and second lines. The electrical state of the switching transistors can be set independently and changeably, under the control of row and column decoders, to specify a desired wiring pattern of the function blocks by having the shortest signal transmission paths of the first and second wiring lines through the hardware as in the case of a custom LSI, thereby realizing the desired custom-made LSI.

Semiconductor integrated circuit device

A method of manufacturing a semiconductor memory device having a trench memory capacitor. First masks are formed on an element forming region of a semiconductor substrate formed of the element forming region and an element isolation region. A film formed of a different material from that of the first masks is deposited and is etched by anisotropic dry etching to leave second masks around the first mask. The semiconductor substrate is selectively etched using the first and second masks as an etching mask so as to form a first groove in the element isolation region. An insulation film is buried in the first groove. A portion of the first mask, formed at least above memory capacitor forming regions in the element forming region, is removed by etching, thereby forming a third mask on a portion excluding the memory capacitor forming region. The semiconductor substrate is selectively etched by using the second and third masks and the insulation film buried in the first groove as an etching mask so as to form second grooves in the respective memory capacitor forming regions. A distance between the first and second grooves is defined by the second masks in a self-alignment manner. A capacitor electrode is formed in the second grooves through a gate insulation film.

Method of manufacturing semiconductor memory device having trench memory

A method to prevent dielectric breakdown of a thin gate insulating film of a memory cell capacitor of a dynamic semiconductor memory device such as a dynamic random access memory during fabrication of the memory. A diffusion layer of an n-conductivity type is formed on a predetermined surface region of a semiconductor substrate of a p-conductivity type so as to form a p-n junction. Then, there is formed a polycrystalline semiconductor layer which corresponds to a gate electrode and which is connected to the thin gate insulating film and partially contacts the diffusion layer. Thus the polycrystalline semiconductor layer is electrically connected to the substrate through a diode region which is formed of the p-n junction. The polycrystalline semiconductor layer is then etched in a reactive ion etching step, and any abnormal charges stored in the thin gate insulation layer during the reactive etching step are immediately discharged to the substrate.

Dynamic semiconductor memory and manufacturing method thereof

A method of manufacturing a semiconductor device which comprises the steps of forming an interconnection layer through an insulating film on a semiconductor substrate, and connecting the diffusion interconnection region in the surface portion of said substrate to said interconnection layer by growing a metal or metal semiconductor compound on the surface of said substrate and the interconnection layer.

Method of manufacturing a semiconductor device

Provided is a stacked semiconductor device wherein a plurality of semiconductor layers integrated with semiconductor elements are stacked with an insulating layer interposed between two adjacent of said semiconductor layers. This semiconductor device has one or more inclined faces extending over two or more of said semiconductor layers. These inclined faces are formed thereon with an interconnection layer or semiconductor element for effecting the transmission and reception of signals between circuits, having said semiconductor elements, formed in the different semiconductor layers, through another insulating layer.

Stacked semiconductor device with sloping sides

A method for manufacturing integrated circuit devices wherein semiconductor elements are isolated by insulation material comprising the following steps of: (a) providing a mask pattern on a predetermined semiconductor element region of a semiconductor substrate; (b) introducing by first ion-implantation impurities of the same conductivity type as that of the substrate into the substrate using the mask pattern as an ion-implantation mask; (c) etching the substrate and forming a groove using the mask pattern as an etching mask in a manner that part of the impurities remain at least under the mask pattern in the side walls of the groove; (d) introducing by second ion-implantation impurities of the same conductivity type as that of the substrate through the groove into the substrate; (e) burying insulation material in the groove; and (f) forming a semiconductor element on the predetermined semiconductor element region.

Method of forming planar isolation regions having field inversion regions

A method of forming a flat field region in a semiconductor substrate, which comprises forming a recess in the substrate, forming a covering on the whole surface of the substrate with a first insulating film such as plasma CVD SiO.sub.2 film which gives a layer at the side portion of the recess more rapidly etchable as compared with other portions, selectively removing the layer at the side portion to thereby form a V-shaped groove between the side of the recess and the first insulating film, and filling the V-shaped groove with a second insulating material so as to obtain a flat field region which is flush with the surface of an element-forming re

Method for manufacturing semiconductor device

A method for manufacturing an MOS FET includes a step of forming a p.sup.+ -type layer in a p-type substrate by injecting ions into the substrate through a field oxide film using a mask layer and removing the portion of the field oxide film under the mask layer.

Growing community of inventors

Yokohama, Japan

Tadashi Shibata