Hitachi, Ltd.

Hitachi Microcomputer Engineering, Ltd.

Other

Hitachi Vlsi Engineering Corp.

Hitachi Cable, Inc.

Hitachi Microcomputer Eng. Ltd.

Hitachi Microcomputer

Tadahiko Nishimukai

Atsushi Hasegawa

Makoto Hanawa

Kunio Uchiyama

Ikuya Kawasaki

Masaru Matsumura

Makoto Suzuki

Osamu Nishii

Katsuhiro Shimohigashi

Katsuyuki Sato

Kanji Oishi

Yoshimune Hagiwara

Hirokazu Aoki

Susumu Hatano

Takashi Kikuchi

Hiroshi Fukuta

Yasuhiko Saigou

Haruo Koizumi

Yoshifumi Takamoto

Satoshi Yoshida

Hideo Maejima

Takeshi Aimoto

Susumu Narita

Hideo Nakamura

Takehisa Hayashi

Kouki Noguchi

Hiroyuki Itoh

Noboru Masuda

Hisayuki Higuchi

Takao Mori

Tetsuhiko Okada

Suguru Tachibana

Noboru Yamaguchi

Kenji Yamaguchi

Hiroyuki Masuda

Shigehiro Kamejima

Minoru Ishii

A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the instruction address, an instruction decoder decoding an instruction from said cache memory corresponding to an instruction address from said instruction address generator, an operand address generator generating an operand address in response to an output signal of said instruction decoder, and an operand cache memory having entries each storing an operand address and operand data corresponding to the operand address in its entry. The data processor executes an instruction that makes entries in both of said instruction cache memory and said operand cache memory ineffective.

Data processor capable of executing an instruction that makes a cache memory ineffective

A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer system) accessible by another processing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) accessible by the central processing system. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address is not for the part accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.

Data processing system with an enhanced cache memory control

A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executor executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

Data processor

A multiprocessor system of the present invention has an address bus, a data bus, first and second processors, four access queues, first and second arbiters, and a shared memory divided into four banks. The four access queues are constituted by first-in first-out memories for buffering a plurality of access-request addresses transmitted through the address bus. When a processor requires data from the memory bank, the processor sends a processor ID with a data access request. When the memory bank sends data in return, the memory bank outputs the processor ID of the request originator with the required data. Even if continuous access requests are addressed to one bank of the shared memory, a succeeding access requested need not wait for a previous access request to be finished. According, the throughput of the system can be improved greatly. The first and second arbiters serve to decide ownership of buses.

Multiprocessor system having distinct data bus and address bus arbiters

A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) is for a part (such as a status register in the above-mentioned microcomputer system) accessible by another procesing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) accessible by the central processing system. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address is not for the part accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.

Data processing system which controls operation of cache memory based

A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instructioon is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output the instruction to be executed. An instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

Purge control for ON-chip cache memory

A multiprocessor system includes an address bus 170, a data bus 180, processors 110 and 120, access queues 135 and 145, shared memories 130 and 140, and lock control circuits 500 and 510. Particularly, a lock-in indicative flag register 501 is provided in the lock control circuit 500. While an operand cache 112 in one processor 110 is making a lock access to a predetermined address of the shared memory 130, the flag register 501 is set on the basis of a lock command signal 260 so that an access of an instruction cache 122 in another processor 120 to the predetermined address of the shared memory 130 is prohibited but an access to a different address is permitted at the time of the lock access. After the lock access is released, the lock control circuit 500 accepts an access to the predetermined address.

Multiprocessor system having a processor invalidating operand cache when

A data processor for executing instructions using operand data stored in a main memory includes an instruction control unit having a first associative memory storing instructions read out from the main memory. The data processor also includes an instruction controller reading out an instruction from the first associative memory when the instruction is present in the first associative memory and reading an instruction from the main memory when the instruction is not present in the first associative memory. The controller also has as an output; and an instruction execution unit has a second associative memory storing operand data read out from the main memory. An instruction executioner executes the instruction by using operand data read out from the second associative memory when the operand data is present in the second associative memory and from the main memory when the operand data is not present in the second associative memory.

Data processor with on-chip cache memory and purge controller responsive

A detect circuit is provided in a system such as an I/O mapped microcomputer system in order to detect whether or not an access address for a read access request generated by a central processing unit (CPU) corresponds to an area (such as a status register in the above-mentioned microcomputer system), which is accessible by another processing device, such as an I/O device, within the entire storage area (such as a main storage and the status register) which is accessible by the central processing system is performed. If data to be fetched for an instruction executed by the central processing unit is not found in a cache memory, the data is fetched from the entire storage area. A write circuit is provided which writes the fetched data into the cache memory when the detect circuit shows that the access address does not correspond to that area accessible by the other processing device within the entire storage area, but otherwise the write circuit does not write the fetched data into the cache memory.

Ring systolic array system for synchronously performing matrix/neuron

A method of assembling a semiconductor chip on a tape carrier has the steps of stacking, on a film carrier having a first group of metal leads, another film carrier having a second group of metal leads and bonding the two film carriers together by adhesive to form a laminated structure. The first and second groups of metal leads are so disposed that they do not contact and do not cross one another. The tips of the metal leads of the two groups are bonded to the electrodes on the semiconductor chip. The metal leads are formed in advance on the corresponding film carriers by etching. By stacking the plurality of film carriers, the connection pitch can be reduced while eliminating a necessity for reducing the thickness of each lead.

Metal lead-film carrier assembly having a plurality of film carriers,

An intra-LSI clock distribution circuit which includes a main distribution circuit, a plurality of intra-block clock distribution circuitries, feedback wires provided in association with each of blocks and each connected to one of plural block-based clock signal wires within the associated block and the intra-block distribution circuitry of the associated block for feeding back the intra-block clock signal distributed to a given one of circuit elements connected to the intra-block clock signal wires to the intra-block clock distribution circuitry of that block. The intra-block clock distribution circuitry in each of the blocks responds to the block-destined clock signal supplied to the associated block via one of the block-based clock signal wires connected thereto and the intra-block clock signals fed back via the feedback wires in the associated block to thereby generate a plurality of intra-block clock signals having respective phases which depend on differences in phase between the block-destined clock signal and the fed-back intra-block clock signals.

Intra-LSI clock distribution circuit

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Sagamihara, Japan

Tadahiko Nishimukai