Macronix International Co., Ltd.

Ta-Hone Yang

Kuang-Chao Chen

Tuung Luoh

Ling-Wuu Yang

Hsiang-Chou Liao

An Chyi Wei

Ling-Wu Yang

I-Jen Huang

Chi-Min Chen

Nan-Tsu Lian

Che-Lun Hung

Sheng-Yuan Chang

A method for detecting defects of wafer by wafer sort is introduced. In the method, a wafer sort testing apparatus is used to obtain a DTL or ADART result, wherein a plurality of repaired sites in a wafer is highlighted according to the DTL or ADART result. A plurality of physical locations of the repaired sites is then output. An analysis equipment is used to match the physical locations with a graphic data system (GDS) design layout coordinate of the wafer so as to generate a data correlating with defects at the repaired sites.

Method and system for detecting defects of wafer by wafer sort

A method for measuring a surface structure of a chip or a wafer is provided that includes obtaining an image of the surface structure of the chip, and then performing an image extraction on the image to convert the extracted image into a first circuit design file. A standard image is selected to convert into a second circuit design file, and then the standard image and at least one target in the image are compared to obtain a difference therebetween. According to the difference, at least one data of the surface structure may be made, wherein the data is selected from one of line edge roughness (LER), line width roughness (LWR), contact edge roughness (CER), critical dimension (CD), bias, 3 sigma, maximum, minimum, etc. and repeating defect.

Method for measuring and analyzing surface structure of chip or wafer

Present example embodiments relate generally to methods of fabricating a three-dimensional gate-all-around (GAA) vertical gate (VG) semiconductor structure comprising providing a substrate; forming a plurality of layers having alternating first insulative material layers and second insulative material layers over the substrate; identifying bit line and word line locations for the formation of bit lines and word lines; removing at least a portion of the plurality of layers outside of the identified bit line and word line locations, each of the removed portions extending through the plurality of layers to at least a top surface of the substrate; forming a vertical first insulative material structure in the removed portions; performing an isotropic etching process to remove the second insulative material from the second insulative material layers; forming bit lines in the second insulative material layers within the identified bit line locations; and forming word lines in the identified word line locations.

Method of fabricating three-dimensional gate-all-around vertical gate structures and semiconductor devices, and three-dimensional gate-all-round vertical gate structures and semiconductor devices thereof

Present example embodiments relate generally to methods for fabricating semiconductor devices comprising forming an initial stack of alternating insulative and conductive layers over a substrate, identifying a plurality of bit line locations and word line locations for the initial stack, including a first bit line location and a first word line location, and forming, from the initial stack, a vertical arrangement of bit lines in the first bit line location, the vertical arrangement of bit lines having opposing sidewalls. The method further comprises forming a word line by forming a thin conductive layer over selected sections of the opposing sidewalls, the selected sections of the opposing sidewalls being sections within the first word line location. The forming the word line further comprises depositing conductive material adjacent to each thin conductive layer, the deposited conductive material in direct contact with the thin conductive layer.

Method of fabricating deep trench semiconductor devices, and deep trench semiconductor devices

An etching method is disclosed. A substrate is provided. An etching is performed to form at least one opening in the substrate. An auxiliary etching layer is formed in the opening to cover at least one etching residue. The auxiliary etching layer includes a media, a carrier and an etching component encapsulated by the carrier. A treatment process is performed to the auxiliary etching layer. The treatment process includes applying an energy to the auxiliary etching layer or exposing the auxiliary layer to a gas, so that the carrier breaks in the treatment and thereby the etching component is released to etch the etching residue.

Etching method and etching composition

A method for detecting an electrical defect of contact/via plugs is provided. In the method, the contact/via plugs are monitored by an electron-beam (E-Beam) inspection tool to capture an image with a VC (voltage contrast) difference, and then an image extraction is performed on the image with the VC difference, wherein the image extraction is based on Target gray level/back ground gray level. The extracted image is contrasted with a layout design base to obtain a blind contact or Quasi-blind issue of contact/via plugs. A grayscale value of the VC difference having the blind contact or Quasi-blind issue is compared with a determined range of grayscale value to determine whether the VC difference is abnormal.

Method for detecting an electrical defect of contact/via plugs

An electron beam (E beam) inspection optimization is provided, in which a plurality of initial inspection regions in a chip are obtained, wherein a center of each of the initial inspection regions is a defect point. Thereafter, reset inspection regions are regenerated without overlap, wherein each of the reset inspection regions is within a scope covered by a field of view (FOV) and the scope contains at least one of the defect points. Afterwards, a center of the reset inspection region is transferred into an inspection center, and then an E beam inspection is performed on the inspection center.

Electron beam inspection optimization

A method of detecting bitmap failure associated with physical coordinates is provided. In the method, data of wafer mapping inspection are obtained first, and the data include images of defects in each of layers within a wafer and a plurality of physical coordinates of the defects. Thereafter, a bitmap failure detection is performed to obtain digital coordinates of failure bits within the wafer. The digital coordinates are converted into a plurality of physical locations, and the physical locations are overlapped with the physical coordinates so as to rapidly obtain correlations between the failure bits and the defects.

Method of detecting bitmap failure associated with physical coordinate

Described is a method for improving the flatness of a layer deposited on a doped polycrystalline layer, which includes reducing the grain size of the polycrystalline layer to decrease the out-diffusion amount of the dopant from the polycrystalline layer, and/or reducing the amount of the out-diffusing dopant on the surface of the polycrystalline layer.

Method for improving flatness of a layer deposited on polycrystalline layer

A method of predicting product yield may include determining defect characteristics for a product based at least in part on inspection data associated with critical layers of the product, determining yield loss for each of the critical layers, and estimating product yield based on the determined yield loss of the critical layers. A corresponding apparatus is also provided.

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Hsinchu, Taiwan

Ta-Hone Yang