Chips and Technologies, Llc.

T Dean Skelton

Pat Y Hom

A design of logic circuitry to be tested is divided into one or more discrete logic modules usable in other designs of circuitry. An automated test pattern generator (ATPG) program and its tools are applied to the discrete module while not also being applied to the remainder of the logic circuitry, with the result that an ATPG pattern is provided for the module. When the module is reused in another design of logic circuitry, the ATPG pattern is also reusable in such other design.

Module level scan testing

A method of generating a graphical image, such as a font, is described in which expansion data for an image portion that is not to be written is never added to source data for such portion.

Growing community of inventors

San Jose, CA, United States of America

T Dean Skelton