Taiwan Semiconductor Manufacturing Comp. Ltd.

Szu Wei Lu

Jing-Cheng Lin

Shin-Puu Jeng

Chen-Hua Douglas Yu

Chih-Wei Wu

Po-Hao Tsai

Ying-Ching Shih

Clinton Chao

Jui-Pin Hung

Ying Ching Shih

Mirng-Ji Lii

Cheng-Lin Huang

Chung Yu Wang

Shih Ting Lin

I-Ting Chen

Hsin-Hui Lee

Tjandra Winata Karta

Jerry Tzou

Li-Chung Kuo

Kung-Chen Yeh

Ying-Da Wang

Chin-Fu Kao

Chin-Chuan Chang

Chien-Hsiun Lee

Kuo-Chin Chang

Ming-Chung Sung

Ann Luh

Chen-Shien Chen

Shang-Yun Hou

Weng-Jin Wu

Hua-Shu Ivan Wu

Yi-Chao Mao

Nai-Wei Liu

Mark Shane Peng

Long Hua Lee

Chao-Shun Hsu

I-Hsuan Peng

Mickey Ken

The present disclosure provides a manufacturing method of a semiconductor packaging, including forming a redistribution layer (RDL) on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL. The present disclosure also provides a manufacturing method of a package-on-package (PoP) semiconductor structure, including forming a first redistribution layer (RDL) on a polymer-based layer of a carrier, defining an active portion and a dummy portion of the first RDL, placing a semiconductor die over the dummy portion of the first RDL, a back side of the semiconductor die facing the first RDL, forming a second RDL over a front side of the semiconductor die, the front side having at least one contact pad, and attaching a semiconductor package at the back side of the semiconductor die.

Semiconductor package

A flux residue cleaning system includes first and second immersion chambers, first and second spray chambers, and a drying chamber. The first immersion chamber softens an outer region of a flux residue formed around microbumps interposed between a wafer and a die when the wafer is immersed in a first chemical. The first spray chamber removes the outer region of the flux residue when the wafer is impinged upon by a first chemical spray in order to expose an inner region of the flux residue. The second immersion chamber softens the inner region of the flux residue when the wafer is immersed in a second chemical. The second spray chamber removes the inner region of the flux residue when the wafer is impinged upon by a second chemical spray in order to clean the wafer to a predetermined standard. The drying chamber dries the wafer.

Flux residue cleaning system and method

A semiconductor package includes an interposer chip having a frontside, a backside, and a corner area on the backside defined by a first corner edge and a second corner edge of the interposer chip. A die is bonded to the frontside of the interposer chip. At least one dam structure is formed on the corner area of the backside of the interposer chip. The dam structure includes an edge aligned to at least one the first corner edge and the second corner edge of the interposer chip.

Die-on-interposer assembly with dam structure and method of manufacturing the same

Packages, packaging methods, and packaged semiconductor devices are disclosed. In some embodiments, a package for a semiconductor device includes a redistribution layer (RDL) and a plurality of through package vias (TPV's) coupled to the RDL. Each of the plurality of TPV's comprises a first region proximate the RDL and a second region opposite the first region. The first region comprises a first width, and the second region comprises a second width. The second width is greater than the first width.

Packages, packaging methods, and packaged semiconductor devices

Semiconductor package manufacturing method

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages are disclosed. In one embodiment, a semiconductor device includes an insulating material layer having openings on a surface of a substrate. One or more insertion bumps are disposed over the insulating material layer. The semiconductor device includes signal bumps having portions that are not disposed over the insulating material layer.

Semiconductor devices, methods of manufacture thereof, and semiconductor device packages

A bottom chase and a top chase of a molding system form a cavity to house a molding carrier and one or more devices. The molding carrier is placed in a desired location defined by a guiding component. The guiding component may be entirely within the cavity, or extend above a surface of the bottom chase and extend over a contacting edge of the top chase and the bottom chase, so that there is a gap between the edge of the top chase and the edge of the molding carrier which are filled by molding materials to cover the edge of the molding carrier. Releasing components may be associated with the top chase and/or the bottom chase, which may be a plurality of tape roller with a releasing film, or a plurality of vacuum holes within the bottom chase, or a plurality of bottom pins with the bottom chase.

Molding wafer chamber

Warpage and breakage of integrated circuit substrates is reduced by compensating for the stress imposed on the substrate by thin films formed on a surface of the substrate. Particularly advantageous for substrates having a thickness substantially less than about 150 &#x3bc;m, a stress-tuning layer is formed on a surface of the substrate to substantially offset or balance stress in the substrate which would otherwise cause the substrate to bend. The substrate includes a plurality of bonding pads on a first surface for electrical connection to other component.

Methods of manufacturing an integrated circuit having stress tuning layer

A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

Sawing underfill in packaging processes

Flexible structures and method of providing a flexible structure are disclosed. In some embodiments, a method of providing a flexible structure includes: providing a flex substrate having a device bonded to a first side of the flex substrate; and attaching a rigid layer to a second side of the flex substrate opposite the first side using an adhesive layer.

Warpage control for flexible substrates

Methods and tools for de-bonding and cleaning substrates are disclosed. A method includes de-bonding a surface of a first substrate from a second substrate, and after de-bonding, cleaning the surface of the first substrate. The cleaning comprises physically contacting a cleaning mechanism to the surface of the first substrate. A tool includes a de-bonding module and a cleaning module. The de-bonding module comprises a first chuck, a radiation source configured to emit radiation toward the first chuck, and a first robot arm having a vacuum system. The vacuum system is configured to secure and remove a substrate from the first chuck. The cleaning module comprises a second chuck, a spray nozzle configured to spray a fluid toward the second chuck, and a second robot arm having a cleaning device configured to physically contact the cleaning device to a substrate on the second chuck.

De-bonding and cleaning process and system

A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

Method of three dimensional integrated circuit assembly

The present disclosure provides a semiconductor structure. The semiconductor structure includes a carrier, a first redistribution layer (RDL) over the carrier, a semiconductor die over the first RDL, an adhesive layer between the semiconductor die and the first RDL, and a molding compound encapsulating the first RDL, the semiconductor die, and the adhesive layer. The first RDL includes at least one pattern electrically isolated from any component of the semiconductor structure. The present disclosure provides a method for manufacturing a semiconductor structure discussed herein. The method includes forming an RDL on a carrier, defining an active portion and a dummy portion of the RDL, and placing a semiconductor die over the dummy portion of the RDL.

Semiconductor package and manufacturing method thereof

Growing community of inventors

Hsin-Chu, Taiwan

Szu Wei Lu