Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

Szu-Wei Lu

Ying-Ching Shih

Jing-Cheng Lin

Chih-Wei Wu

Li-Hui Cheng

Chen-Hua Douglas Yu

Chin-Fu Kao

Tsung-Fu Tsai

Pu Wang

Chih-Chien Pan

Shih-Ting Lin

Chin-Chuan Chang

Chih-Hao Chen

Li-Chung Kuo

Chi-Hsi Wu

Shih Ting Lin

Kung-Chen Yeh

Hsien-Ju Tsou

Chen-Hsuan Tsai

Yi-Chao Mao

Shang-Yun Hou

Shin-Puu Jeng

Long Hua Lee

Hsien-Pin Hu

Wen-Hsin Wei

Ping-Yin Hsieh

Jiun-Ting Chen

I-Ting Huang

Wen-Chih Chiou

Feng-Cheng Hsu

Kuan-Yu Huang

Jung-Hua Chang

Yu-Wei Chen

Chih-Yuan Chien

Mirng-Ji Lii

An-Jhih Su

Ruoh-Huey Uang

Ying-Da Wang

Shu-Hang Liao

Ling-Chen Kung

Hung-Wei Tsai

Hou-Ju Huang

Po-Hao Tsai

Kuo-Chiang Ting

Chien-Hsiun Lee

Clinton Chao

Weiming Chris Chen

Hsu-Tien Hu

Kun-Tong Tsai

Yi-Jung Chen

Yen-Yao Chi

Der-Chyang Yeh

Kuo-Chung Yee

Yu-Hung Lin

Hsin-Hui Lee

Sao-Ling Chiu

Ming-Shih Yeh

Ying-Nan Wen

Kuo-Chin Chang

Ming Huei Lu

Ping-Kang Huang

Ting-Yu Yeh

Tjandra Winata Karta

Jyh-Rong Lin

Hung-Chih Chen

Chia-Nan Yuan

Po-Yuan Cheng

Kuo-Chuan Chen

Cheng-Chieh Li

Chih-Ta Shen

Chung-Chieh Ting

Hung-Yu Chen

Yu-Hsun Wang

Chen-Shien Chen

Jiun Yi Wu

Jui-Pin Hung

Pei-Haw Tsao

Hsing-Kuo Hsia

Chun-Yi Kuo

Chung Yu Wang

Han-Liang Tseng

Hsin-Chien Huang

Chung-Yu Wang

Tsung-Yao Chu

I-Ting Chen

Ann Luh

Jerry Tzou

Wei-An Tsao

I-Hsuan Peng

Long-Hua Lee

Ruoh-Huey Wang

Yi Chou

Jeh-Yin Chang

Chen Chiang Yu

An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.

Integrated circuit structure, and method for forming thereof

A semiconductor package including a cooling system and a method of forming are provided. The semiconductor package may include an interposer, one or more package components bonded to the interposer, an encapsulant on the interposer, and a cooling system over the one or more package components. The cooling system may include one or more metal layers on top surfaces of the one or more package components, first metal pins on the one or more metal layers, second metal pins, wherein each of the second metal pins may be bonded to a corresponding one of the first metal pins by solder, and a first lid over the second metal pins, wherein the first lid may include openings.

Semiconductor package and method

A package structure includes a substrate, a first die, a second die, a first thermal conductive layer, a heat spreader and a second thermal conductive layer. The first die and the second die are bonded to the substrate. The first thermal conductive layer is inserted between the first die and the second die. The heat spreader is disposed on the substrate to cover the first die and the second die. The second thermal conductive layer is different from the first thermal conductive layer, wherein the second thermal conductive layer is disposed between the first thermal conductive layer and the heat spreader.

Package structures

In an embodiment, a device includes: an interposer; a first integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a second integrated circuit device bonded to the interposer with dielectric-to-dielectric bonds and with metal-to-metal bonds; a buffer layer around the first integrated circuit device and the second integrated circuit device, the buffer layer including a stress reduction material having a first Young's modulus; and an encapsulant around the buffer layer, the first integrated circuit device, and the second integrated circuit device, the encapsulant including a molding material having a second Young's modulus, the first Young's modulus less than the second Young's modulus.

Integrated circuit package and method

An embodiment is a package including a package substrate and a package component bonded to the package substrate, the package component including an interposer, an optical die bonded to the interposer, the optical die including an optical coupler, an integrated circuit die bonded to the interposer adjacent the optical die, a lens adapter adhered to the optical die with a first optical glue, a mirror adhered to the lens adapter with a second optical glue, the mirror being aligned with the optical coupler of the optical die, and an optical fiber on the lens adapter, a first end of the optical fiber facing the mirror, the optical fiber being configured such that an optical data path extends from the first end of the optical fiber through the mirror, the second optical glue, the lens adapter, and the first optical glue to the optical coupler of the optical die.

Integrated circuit package and method of forming same

A semiconductor package includes a first semiconductor die, a second semiconductor die, a semiconductor bridge, an integrated passive device, a first redistribution layer, and connective terminals. The second semiconductor die is disposed beside the first semiconductor die. The semiconductor bridge electrically connects the first semiconductor die with the second semiconductor die. The integrated passive device is electrically connected to the first semiconductor die. The first redistribution layer is disposed over the semiconductor bridge. The connective terminals are disposed on the first redistribution layer, on an opposite side with respect to the semiconductor bridge. The first redistribution layer is interposed between the integrated passive device and the connective terminals.

Semiconductor package and manufacturing method thereof

A method includes attaching semiconductor devices to an interposer structure, attaching the interposer structure to a first carrier substrate, attaching integrated passive devices to the first carrier substrate, forming an encapsulant over the semiconductor devices and the integrated passive devices, debonding the first carrier substrate, attaching the encapsulant and the semiconductor devices to a second carrier substrate, forming a first redistribution structure on the encapsulant, the interposer structure, and the integrated passive devices, wherein the first redistribution structure contacts the interposer structure and the integrated passive devices, and forming external connectors on the first redistribution structure.

A semiconductor package includes a first integrated circuit, a plurality of first through vias and a plurality of fin-shaped through vias. The first through vias surround the first integrated circuit. The fin-shaped through vias are physically connected to the first through vias respectively, wherein the first through vias are disposed between the first integrated circuit and the fin-shaped through vias.

Semiconductor packages

A package structure including an interposer, at least one semiconductor die and an insulating encapsulation is provided. The interposer includes a semiconductor substrate and an interconnect structure disposed on the semiconductor substrate, the interconnect structure includes interlayer dielectric films and interconnect wirings embedded in the interlayer dielectric films, the semiconductor substrate includes a first portion and a second portion disposed on the first portion, the first interconnect structure is disposed on the second portion, and a first maximum lateral dimension of the first portion is greater than a second maximum lateral dimension of the second portion. The at least one semiconductor die is disposed over and electrically connected to the interconnect structure. The insulating encapsulation is disposed on the first portion, wherein the insulating encapsulation laterally encapsulates the least one semiconductor die and the second portion.

Package structure and method of fabricating the same

In an embodiment, a device bonding apparatus is provided. The device bonding apparatus includes a first process station configured to receive a wafer; a first bond head configured to carry a die to the wafer, wherein the first bonding head includes a first rigid body and a vacuum channel in the first rigid body for providing an attaching force for carrying the die to the wafer; and a second bond head configured to press the die against the wafer, the second bond head including a second rigid body and an elastic head disposed over the second rigid body for pressing the die, the elastic head having a center portion and an edge portion surrounding the center portion, the center portion of the elastic head having a first thickness, the edge portion of the elastic head having a second thickness, the second thickness being greater than the second thickness.

Device bonding apparatus and method of manufacturing a package using the apparatus

A manufacturing method of a package structure includes: forming a first package component over a temporary carrier, wherein the first package component comprises a semiconductor die encapsulated by an insulating encapsulation material that comprises a base layer and a plurality of fillers inside the base layer; de-bonding the temporary carrier to expose a rear side of the semiconductor die, wherein during the de-bonding, a portion of the fillers is accessibly revealed from the base layer to form an insulating encapsulation; forming a metallic layer on the rear side of the semiconductor die and the portion of the fillers of the insulating encapsulation; and coupling a heat dissipating component to the first package component at least through the metallic layer.

Package structure and manufacturing method thereof

A semiconductor structure including an integrated circuit die and conductive bumps is provided. The integrated circuit die includes bump pads. The conductive bumps are disposed on the bump pads. Each of the conductive bumps includes a first pillar portion disposed on one of the bump pads and a second pillar portion disposed on the first pillar portion. The second pillar portion is electrically connected to one of the bump pads through the first pillar portion, wherein a first width of the first pillar portion is greater than a second width of the second pillar portion. A package structure including the above-mentioned semiconductor structure is also provided.

Package structure including stacked pillar portions and method for fabricating the same

A package assembly may include a package substrate, a package lid attached to the package substrate and including a plate portion, an outer foot extending from the plate portion, and an inner foot extending from the plate portion inside the outer foot, and an adhesive that adheres the outer foot to the package substrate and the inner foot to the package substrate.

Package assembly including a package lid having an inner foot and methods of making the same

A package includes a laser diode includes a bonding layer; a first dielectric layer over the laser diode, wherein the first dielectric layer is directly bonded to the bonding layer of the laser diode; a first silicon nitride waveguide in the first dielectric layer, wherein the first silicon nitride waveguide extends over the laser diode; a second dielectric layer over the first silicon nitride waveguide; a silicon waveguide in the second dielectric layer; an interconnect structure over the silicon waveguide; and conductive features extending through the first dielectric layer and the second dielectric layer to electrically contact the interconnect structure.

Photonic package and method of manufacture

An inspection apparatus for inspecting a semiconductor workpiece includes a testing stage, a first seal member, a testing clamp, a second seal member, a semiconductor workpiece, and a transducer. The testing stage has a cavity. The first seal member is disposed in the cavity. The first seal member is attached to a sidewall of the cavity. The testing clamp is movably coupled to the testing stage. The second seal member is attached to the testing clamp. The semiconductor workpiece is held between the testing stage and the testing clamp by the first seal member and the second seal member. The transducer is movably disposed above the testing stage.

Inspection apparatus, manufacturing method of integrated circuit, and inspection method

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Hsinchu, Taiwan

Szu-Wei Lu