Taiwan Semiconductor Manufacturing Comp. Ltd.

Szu-Ping Tung

Chih-Chien Chi

Ching-Hua Hsieh

Huang-Yi Huang

Shing-Chyang Pan

Jen Hung Wang

Hung-Wen Su

Szu-Hua Wu

Jung-Tang Wu

Meng-Yu Wu

Tze-Liang Lee

Chung-Chi Ko

Yu-Kai Lin

Mei-Ling Chen

Chun-Kai Chen

Ching-Yu Chang

Hua-Tai Lin

Yi-Nien Su

Neng-Jye Yang

Han-Wei Wu

Wei-De Ho

Meng-Jung Lee

Pei-Sheng Tang

Lan-Hsin Chiang

Dian-Hau Chen

Hsiang-Ku Shen

Minghsing Tsai

Jung-Hau Shiu

Chen-Chiu Huang

Guan-Yao Tu

Wen-Jiun Liu

Jen-Hung Wang

Ssu-Yu Ho

Wen-Tzu Chen

A semiconductor device includes a substrate, a first conductive feature over a portion of the substrate, and an etch stop layer over the substrate and the first conductive feature. The etch stop layer includes a silicon-containing dielectric (SCD) layer and a metal-containing dielectric (MCD) layer over the SCD layer. The semiconductor device further includes a dielectric layer over the etch stop layer, and a second conductive feature in the dielectric layer. The second conductive feature penetrates the etch stop layer and electrically connects to the first conductive feature.

Etch stop layer for semiconductor devices

Embodiments utilize a photoetching process in forming a patterned target layer. After forming a patterned mandrel layer and spacer layer over the patterned mandrel layer, a bottom layer of a photomask is deposited using a chemical vapor deposition process to form an amorphous carbon film. An upper layer of the photomask is used to pattern the bottom layer to form openings for a reverse material. The reverse material is deposited in the openings of the bottom layer, the bottom layer providing both a mask and template function for the reverse material.

Film deposition for patterning process

A method for evaluation of thin film non-uniform stress using high order wafer warpage, the steps including measuring a net wafer warpage across a wafer area due to thin film deposition, fitting a two dimensional low-order polynomial to the wafer warpage measurements and subtracting the low-order polynomial from the net wafer warpage across the wafer area.

Method for evaluating non-uniform stress

In one exemplary aspect, the present disclosure is directed to a method for lithography patterning. The method includes providing a substrate and forming a target layer over the substrate. A patterning layer is formed by depositing a first layer having an organic composition; depositing a second layer including over 50 atomic percent of silicon; and depositing a photosensitive layer on the second layer. In some implementations, the second layer is deposited by ALD, CVD, or PVD processes.

Patterning material including silicon-containing layer and method for semiconductor device fabrication

A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.

Method of forming an interconnect structure having an air gap and structure thereof

A semiconductor device includes a transistor structure disposed over a substrate, a first interlayer dielectric (ILD) layer disposed over the transistor structure, a second ILD layer disposed over the first ILD layer, and a first resistor wire disposed on the second ILD layer, and a second resistor wire disposed on the second ILD layer. A sheet resistance of the first resistor wire is different from a sheet resistance of the second resistor wire.

Method of manufacturing a semiconductor device and a semiconductor device

A structure includes a substrate, a transistor, a contact, an oxygen-free etch stop layer, an oxygen-containing etch stop layer, a dielectric layer, and a via. The transistor is on the substrate. The contact is on a source/drain region of the transistor. The oxygen-free etch stop layer spans the contact. The oxygen-containing etch stop layer extends along a top surface of the oxygen-free etch stop layer. The dielectric layer is over the oxygen-containing etch stop layer. The via passes through the dielectric layer, the oxygen-containing etch stop layer, and the oxygen-free etch stop layer and lands on the contact. The memory stack lands on the via.

Memory device and method for fabricating the same

Thin-film non-uniform stress evaluation

A semiconductor structure includes a conductive feature, a first metal-based etch-stop layer over the underlying structure, a metal-free etch-stop layer over the first metal-based etch-stop layer, a second metal-based etch-stop layer over the metal-free etch-stop layer, an interlayer dielectric layer over the second metal-based etch-stop layer, and an interconnect structure extending through the first metal-based etch-stop layer, metal-free etch-stop layer, and the second metal-based etch-stop layer, wherein a bottom portion of the conductive interconnect structure directly contacts the conductive feature. The first metal-based etch-stop layer may include a first metallic component having one of aluminum, tantalum, titanium, or hafnium, and the second metal-based etch-stop layer may include a second metallic component the same as or different from the first metallic component. The first metal-based etch-stop layer and the second metal-based etch-stop layer may both be free of silicon.

Metal-based etch-stop layer

A memory device includes a semiconductor substrate, a first dielectric layer, a metal contact, an aluminum nitride layer, an aluminum oxide layer, a second dielectric layer, a metal via, and a memory stack. The first dielectric layer is over the semiconductor substrate. The metal contact passes through the first dielectric layer. The aluminum nitride layer extends along a top surface of the first dielectric layer and a top surface of the metal contact. The aluminum oxide layer extends along a top surface of the aluminum nitride layer. The second dielectric layer is over the aluminum oxide layer. The metal via passes through the second dielectric layer, the aluminum oxide layer, and the aluminum nitride layer and lands on the metal contact. The memory stack lands on the metal via.

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Taipei, Taiwan

Szu-Ping Tung