Stmicroelectronics S.a.

Commissariat &#xc0; L'&#xc9;nergie Atomique Et Aux &#xc9;nergies Alternatives

Sylvain Majcherczak

Dimitri Soussan

Marc Belleville

Alexandre Valentian

Guy Mabboux

An integrated circuit may include a digital output port including a buffer stage that includes subassemblies of MOSFET transistors. One subassembly may include two pull-up transistors having sources connected to a common high voltage, and having drains connected to a common node connected to the output terminal. Another subassembly may include pull-down transistors having sources connected to a common low voltage, and having drains connected to the common node. The pull-up and pull-down transistors are formed in a thin semiconductor layer of an FDSOI substrate. The substrate may include a thick semiconductor layer and an oxide layer separating the thin and thick semiconductor layers. Areas of the thick semiconductor layer facing the pull-up and pull-down transistors may be connected to a circuit configured to vary a threshold voltage of the pull-up and pull-down transistors.

Integrated circuit comprising at least one digital output port having an adjustable impedance, and corresponding adjustment method

A method for controlling an output amplification stage comprising first and second complementary SOI-type power MOS transistors, in series between first and second power supply rails, the method including the steps of: connecting the bulk of the first transistor to the first rail when the first transistor is maintained in an off state; connecting the bulk of the second transistor to the second rail when the second transistor is maintained in an off state; and connecting the bulk of each of the transistors to the common node of said transistors, during periods when this transistor switches from an off state to an on state.

Output stage formed inside and on top of an SOI-type substrate

A voltage-level translator circuit including two pairs of branches in parallel, each pair including a low-impedance branch, where the low-impedance branches can be activated or deactivated. A possible application is the voltage level switching of data originating from an integrated circuit.

Level translator circuit

In an integrated circuit, a detection device detects a drop in the supply voltage of the core of the integrated circuit or an excessively slow build-up of this voltage with respect to a supply voltage of the input/output interface circuits of the integrated circuit. Outputs of the interface circuits are set to a high impedance state by the detection device to minimize their power consumption.

Growing community of inventors

St. Pierre d'Allevard, France

Sylvain Majcherczak