International Business Machines Corporation

Minnesota Mining and Manufacturing Company

Globalfoundries Inc.

Lexmark International, Inc.

Sylvain E Ouimet

Luc Gilbert Guerin

David Hirsch Danovitch

Jean-Guy Quintal

Jean Audet

Richard D Langlois

Mark J Kuzawinski

Stephan L Martel

Frederic Beaulieu

Jean Labonte

Guy Robichaud

Stephane Mainville

Bing Dang

Paul Stephen Andry

Russell Alan Budd

Benjamin V Fasano

Jon Alfred Casey

Paul Francis Fortier

Daniel Michael Kuchta

Steven Paul Ostrander

John Saunders Corbin, Jr

Nicholas A Lee

Mitchell S Cohen

Jeannine Madelyn Trewhella

Kenneth Charles Marston

Glen Walden Johnson

Virendra R Jadhav

Jennifer V Muncy

Eric Salvas

Stephen Louis Spanoudis

Marco Gauvin

Isabelle Depatie

Andre Lacerte

Roger A Liptak

Stephane Tremblay

Charles Leon Arvin

Frank Robert Libsch

William Thomas Motsiff

Wayne John Howell

Thomas Anthony Wassick

Kang-Wook Lee

Chirag Suryakant Patel

Tuhin Sinha

Ronald Lee Mendelson

Eric Duchesne

Bhupender Singh

Sylvain Pharand

Martin Beaumier

Claude Blais

Gerald J Scilla

Stephanie Allard

Jean-Francois Drapeau

Chrirag S Patel

Frank F Libsch

An electronic apparatus that includes a first semiconductor chip mounted on a substrate; a second semiconductor chip mounted on the substrate; a spacer attached to the substrate and situated between the first and second semiconductor chips; a lid mounted on the substrate and enclosing the first and second semiconductor chips and the spacer, the spacer having an adhesive material adhesively attached to the lid; and underfill material underneath the first and second semiconductor chips, underneath the spacer and between the spacer and the first and second semiconductor chips.

Electronic apparatus having inter-chip stiffener

A first and second antenna substrate are included in an advanced antenna package. Each antenna substrate includes a respective array of antenna elements disposed on a respective first surface of the substrate. A plurality of stand-off balls disposed between the first surfaces of first and second antenna substrates are bonded to the first surface of the first antenna substrate. A first sub-plurality of the stand-off balls are placed at positions in a peripheral region of the first and second antenna substrates. A second sub-plurality of the stand-off balls are placed at interior positions between antenna elements of the first and second antenna substrates. A plurality of adhesive pillars are disposed between and bond the first surfaces of first and second antenna substrates at a plurality of discrete selected locations. A first location of the discrete selected locations is in a peripheral region. A second location of the discrete selected locations is at an interior position between antenna elements.

Antenna packaging solution

A first and second antenna substrate are included in an advanced antenna package. Each antenna substrate includes a respective array of antenna elements disposed on a respective first surface of the substrate. A plurality of stand-off balls disposed between the first surfaces of first and second antenna substrates are bonded to the first surface of the first antenna substrate. A first sub-plurality of the stand-off balls are placed at positions in a peripheral region of the first and second antenna substrates. A second sub-plurality of the stand-off balls are placed at interior positions between antenna elements of the first and second antenna substrates. A plurality of adhesive pillars are disposed between and bond the first surfaces of first and second antenna substrates at a plurality of discrete selected locations. A first location of the discrete selected locations is in a peripheral region. A second location of the discrete selected locations is at an interior position between antenna elements. A method for fabricating the antenna package is also described.

A flip chip assembly is disclosed that includes a die with die circuitry and a plurality of electrical contacts electrically connected to the die circuitry. A substrate includes electrical contacts that are juxtaposed with and electrically connected to corresponding die electrical contacts. A passive component is disposed between the die and the substrate, and includes a dielectric disposed between a first electrode and a second electrode. The first electrode is electrically connected to a first of the die electrical contacts and a corresponding substrate electrical contact, and the second electrode is electrically connected to a second of the die electrical contacts and a corresponding substrate electrical contact.

Flip chip assembly with connected component

A standoff structure for providing improved interconnects is provided, wherein the structure employs nickel copper alloy or copper structures having increased resistivity.

All intermetallic compound with stand off feature and method to make

A clamping apparatus and method for applying a force to a workpiece during processing includes a base defining a work area. The work area is configured to receive a joined structure including a substrate and a die. A component is positionable in the work area and over the joined structure. An adjustable releasable structure is positionable over the component and the joined structure and includes a resilient mechanism having an inner member for contacting the component to apply an inner downward force to the component. The resilient mechanism also includes outer members for applying an outer downward force to opposing distal edge areas of the substrate. An external downward force is applied to the adjustable releasable structure, such that the inner and outer members apply the inner and outer downward forces to the component and the opposing distal edge areas of the substrate, respectively, during processing of the joined structure.

Laminate peripheral clamping to control microelectronic module BSM warpage

An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

Silicon carrier optoelectronic packaging

A system and method system for achieving mechanical and thermal stability in a multi-chip package. The system utilizes a lid and multiple thermal interface materials. The method includes utilizing a lid on a multi-chip package and utilizing multiple thermal interface materials on the multi-chip package.

Achieving mechanical and thermal stability in a multi-chip package

A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% Oby volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.

Method of removing metallic, inorganic and organic contaminants from chip passivation layer surfaces

A method for reducing the number of wire-bond loop heights which are required in comparison with a total quantity of power and signal rings employed in low profile wire-bond integrated circuit packages. There are also provided low profile wire-bond packages which are produced in accordance with the method pursuant to the invention.

Method to reduce number of wire-bond loop heights versus the total quantity of power and signal rings

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Sylvain E Ouimet