Intel Corporation

Sven Eric Henrichs

Swaminathan Sivakumar

Charles Henry Wallace

Richard E Schenker

Paul Anton Nyhus

Shem Ogadhoh

Ryan Pearman

Christopher Kenyon

Chang Ju Choi

Arvind Sundaramurthy

Harsha Grunes

Cheng-Hsin Ma

Robert H Olshausen

Yulia Korobko

Jose J Garcia

A mask process development having a consistent mask targeting is described. A method includes receiving an integrated circuit (IC) design. A test mask is generated that converts the IC design into one or more physical layouts. A set of one or more sub-resolution assist features (SRAFs) is inserted into the test mask. The set of one or more SRAFs is inserted into one or more other masks, which are derived from the test mask for mask targeting, such that the test mask and the one or more other masks include a same set of the one or more SRAFs.

Consistent mask targeting through standardized drop-in-cells

Techniques are disclosed for using sub-resolution phased assist features (SPAF) in a lithography mask to improve through process pattern fidelity and/or mitigate inverted aerial image problems. The technique also may be used to improve image contrast in non-inverted weak image sites. The use of SPAF in accordance with some such embodiments requires no adjustment to existing design rules, although adjustments can be made to enable compliance with mask inspection constraints. The use of SPAF also does not require changing existing fab or manufacturing processes, especially if such processes already comprehend phased shift mask capabilities. The SPAFs can be used to enhance aerial image contrast, without the SPAFs themselves printing. In addition, the SPAF phase etch depth can be optimized so as to make adjustments to a given predicted printed feature critical dimension.

Lithography mask having sub-resolution phased assist features

Techniques are disclosed for fabricating lithography masks, which include a first level process comprising lithography and etching to form mask frame and in-die areas, and a second level process comprising lithography and etching to form one or more mask features in the in-die area. At least one of the mask features has a smallest dimension in the nanometer range (e.g., 32 nm technology node, or smaller). The techniques may be embodied, for example, in a lithography mask for fabricating semiconductor circuits. In one such example case, the mask includes a frame area and an in-die area formed after the frame area. The in-die area includes one or more mask features, at least one of which has a smallest dimension of less than 100 nm. The mask has a critical dimension bias of less than 20 nm and a structure that comprises a substrate and an absorber layer.

High resolution phase shift mask

In one embodiment, a mask for use in semiconductor processing comprises a first region formed from a first material that is primarily opaque, a second region formed from a second material that is primarily transmissive, and a third region in which at least a portion of the second material is removed to generate a phase shift in radiation applied to the mask.

Lithography masks for improved line-end patterning

A mask or reticle includes a focus test area having a pattern of opaque lines, naked lines, and phase shifting lines. A resulting pattern on a wafer exposed through the focus test area may have a first area of the pattern shifted with respect to a second area of the pattern if the lithography system is out of focus. In some implementations, an area of the pattern may contract or expand if the lithography system is out of focus. An out of focus condition may be determined using a registration tool, scanning electron microscope (SEM), or an interferometer tool (OCD). An out of focus condition may be improved using out of focus information.

Focus detection structure

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Hillsboro, OR, United States of America

Sven Eric Henrichs