Tokyo Shibaura Electric Co., Ltd.

Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Tokyo Shibaura Denki Electric Co., Ltd.

Susumu Kohyama

Yoshihisa Mizutani

Koji Makita

Yoshihide Nagakubo

Nobuhisa Kubota

A semiconductor device, and more particularly, an erasable programmable read only memory has a control gate electrode and a floating gate electrode. The floating gate electrode is formed on one side wall of the control gate electrode through an insulating film.

EEPROM with sidewall control gate

In gas phase growth of a polysilicon layer on a semiconductor substrate, a silicon layer of a single-crystal structure or a structure akin thereto may be formed only on an exposed surface of the substrate surrounded by an insulating film for element isolation by applying an energy beam to the substrate. A semiconductor device obtained by forming such an element as an MOS transistor on the silicon layer is free from any difference in level between an element region and an element isolation region, and hence from snapping or disconnection of any wiring traversing the boundary between those regions.

Method for manufacturing a semiconductor device having regions of

A semiconductor charge transfer device comprising: a semiconductor charge transfer element including a plurality of transfer electrodes on an insulating layer formed on a semiconductor substrate and a detection node formed on the semiconductor substrate; potential barrier means for signal charge packets transfer provided between the final stage cell of the semiconductor charge transfer element and the detection node; and a differential detecting circuit of flip-flop type having a drive transistor directly coupled with the detection node, wherein the potential barrier means provides a potential barrier against the low level of the detection node when the drive transistor is conductive.

Semiconductor charge transfer device having a decoupling gate for

A charge transfer device has a means for grouping a charge transfer section of a semiconductor substrate into a plurality of semiconductor regions each provided with a plurality of charge transfer electrodes and storing a fixed information, predetermined correspondingly to a combination of surface potential levels to be formed at semiconductor subregions under the electrodes on each semiconductor region, in such semiconductor region.

Charge transfer device stored with fixed information

An electrode per bit (E/B) structure type charge transfer device in which N storage cell each consisting of a barrier region and a storage region are driven by N-phase clocks, one of N storage cells being empty and the remaining N-1 cells storing signal charge packets. The N-phase clocks are biased to a low level for storage and pulsed to a high level for transfer. The N storage cells are successively rendered in the transfer mode in the direction opposite to the charge transfer direction so that the empty cell is shifted to the adjacent preceding cell in the direction opposite to the charge transfer direction every time each of the N-phase clocks is pulsed. After one cycle of the N-phase clocks, all the signal charge packets are shifted to the succeeding cells respectively. A multiplexed electrode per bit (ME/B) structure type charge transfer device also is disclosed which employs the E/B structure and is operable by the clocks with small number of phases, providing a CCD memory with a large capacity.

Multi-channel charge coupled transfer device

This multi-level signal charge sensing circuit includes a first capacitor for holding inspected charge, a second capacitor for holding a plurality of reference charge levels and a comparator for comparing potentials produced at the first and second capacitors. As the plurality of reference charge levels, (N-1) charge levels of different known values are prepared. The inspected charge is given to the first capacitor which is reset, and the (N-1) reference charge levels are successively given from the highest or lowest level to the second capacitor which is also reset. The comparator is operated for every step of supplying each reference charge level. Of the successive reference charge supplying steps at an instant between the steps corresponding to 0 and (N-1), the output state of the comparator is inverted, thus supplying digital information representing the inspected charge level. This sensing circuit permits discrimination and sensing or detection of N different inspected charge levels with a single circuit construction.

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Kawasaki, Japan

Susumu Kohyama