International Business Machines Corporation

The State University of New York

Rensselaer Polytechnic Institute

Sushumna Iruvanti

David L Edwards

Raed A Sherif

Hilton T Toy

Shidong Li

Kamal Kumar Sikka

Jeffrey Allen Zitz

Gaetano Paolo Messina

Frank Louis Pompeo

Mark G Courtney

Stephen S Drofitz, Jr

Wei Zou

Gregory Scott Hopper

Albert Joseph Fahey

Charles Frederick Jones

Yves Corfield Martin

Krishna R Tunga

David J Womac

Krishna Gandhi Sachdev

Thomas Anthony Wassick

Lewis Sigmund Goldmann

Anson Jay Call

Glenn Graham Daves

Giulio DiGiacomo

Tuhin Sinha

Jeffrey Thomas Coffin

Michael J Ellsworth, Jr

Theodore Gerard Van Kessel

David Clifford Long

Paul Alfred Lauro

Jeffrey Donald Gelorme

Wayne Martin Moreau

Thomas Weiss

Benjamin V Fasano

Jon Alfred Casey

Stephen L Buchwalter

David L Questad

James A Busby

Bruce Kenneth Furman

Subhash Laxman Shinde

Lester W Herron

Steven Paul Ostrander

Shaji Farooq

Brian Richard Sundlof

Xiaojin Wei

Rajneesh Kumar

Kenneth Charles Marston

David B Goland

Patrick Anthony Coico

William Edward Sablinski

Steve Ostrander

Joel L Plawsky

Randall Jason Werner

Armando S Cammarano

Daniel D Reinhardt

Theodorian Borca-Tasciuc

Deborah Anne Sylvester

Larry D Gross

Marek Andrzej Orlowski

Martin E Klepeis

Stanley J Jasne

Charles Leon Arvin

William Louis Brodsky

Govindarajan Natarajan

Prabjit Singh

Bruce John Chamberlin

Claudius Feger

James John Kelly

Mario John Interrante

William Santiago-Fernandez

David Lewis Gardell

James N Humenik

Peter Jeffrey Brofman

Thomas J Fleischman

Brian W Quinlan

Nihad Hadzic

Mark William Kapfhammer

Randall G Kemink

Robin A Susko

Hsichang Liu

Jennifer V Muncy

Gregg B Monjeau

Jay A Bunt

Eli Ruckenstein

Jiantao Zheng

Hongqing Zhang

Richard D Langlois

Marcus E Interrante

Jason Scott Miller

Ronald L Hering

Mark S Chace

David J Lewison

Chris Muzzy

Philipp K Buchling Rego

Ijeoma M Nnebe

Kevin Drummond

Normand Cote

Rui Wang

Michael J Emmett

Scott A Cummings

A laminate carrier-like module lid including multiple laminate layers of non-conductive materials stacked one atop another, sensor circuitry embedded within the laminate carrier-like module lid, the sensor circuitry providing a continuous electrical circuit surrounding the electronic components of the multi-chip module package, and thermal circuitry embedded within the laminate carrier-like module lid, the thermal circuitry comprising solid copper traces to thermally conduct heat from the electronic components of the multi-chip module package.

Multi chip hardware security module

Moisture-driven degradation of a crack stop in a semiconductor die is mitigated by forming a groove in an upper surface of the die between an edge of the die and the crack stop; entirely filling the groove with a moisture barrier material; preventing moisture penetration of the semiconductor die by presence of the moisture barrier material; and dissipating mechanical stress in the moisture barrier material without presenting a stress riser in the bulk portion of the die. The moisture barrier material is at least one of moisture-absorbing, moisture adsorbing, and hydrophobic.

Mitigating moisture-driven degradation of features designed to prevent structural failure of semiconductor wafers

A technique relates to an electronic package. A substrate is configured to receive a chip. A stiffener is attached to the substrate. The stiffener includes a core material with a first material formed on opposing sides of the core material.

Laminated stiffener to control the warpage of electronic chip carriers

Structural combinations of TIMs and methods of combining these TIMs in semiconductor packages are disclosed. An embodiment forms the structures by selectively metallizing a backside of a semiconductor chip (chip) on chip hot spots, placing a higher performance thermal interface material (TIM) on the metallized hot spots, selectively metalizing an underside of a lid in one or more metalized lid locations, and assembling a lid over the backside of the chip to create an assembly so that metalized lid locations are in contact with the higher performance TIMs. A lower performance TIM fills the region surrounding the higher performance TIM on the underside of the lid enclosing the chips. Disclosed are methods of disposing both solid and dispensable TIMs, curing and not curing the thermal interface, and structures to keep the TIMs in place while assembly the package and compressing dispensable TIMs. Alternative method steps are disclosed, such as: injecting the lower performance TIM through injection holes in a pre-assembled assembly, using solid preform TIMs with cutouts, and using high performance TIM structures that have collapsible rails to prevent lower performance TIM from spilling onto the surface of the higher performance TIM to permit good/bonding.

Hybrid TIMs for electronic package cooling

An integrated circuit (IC) device package includes an IC device connected to an upper surface of the IC device carrier. Due to operation conditions or IC device package makeup, the IC device may warp. The warped IC device may include a convex upper surface. A conformable lid is connected to the IC device and includes an internal chamber and a deformable floor. The deformable floor is able to deform or bend along with the IC device. After deformation, the deformable floor may include a concave lower surface. A uniform bond line thickness of a thermal interface material that connects the IC device and the conformable lid is able to be achieved due to the deformable floor deforming or bending along with the IC device.

Conformal integrated circuit (IC) device package lid

An IC device package includes an IC device that is connected to a lid by a thermal interface material (TIM). A catalyst material is formed upon one or more regions upon an upper surface of the IC device and/or an under surface of the lid. The catalyst material increases the rate of crosslinking of polymer chains of the TIM during TIM curing and/or increases the strength of crosslinks that link polymer chains of the TIM during TIM curing. The catalytically enhanced regions have a higher coefficient of heat transfer relative to non-catalytically enhanced regions. Therefore, the catalytically enhanced regions efficiently transfer heat from the IC device to the lid.

Localized catalyst for enhanced thermal interface material heat transfer

Embodiments of the present invention relate to an heterogenous thermal interface material (TIM). The heterogenous TIM includes two or more different materials. One material has a low elastic modulus, also known as Young's modulus, and is utilized primarily to transfer heat from one component to another component. Another material has a higher elastic modulus and is primarily utilized to bond or connect the corners and/or edges of one component to the other component. The high elastic modulus material is generally located within the heterogenous TIM where TIM strain is or is expected to be high. For example, the high elastic modulus material may be located at the corner and/or edge regions of the heterogenous TIM.

Heterogeneous thermal interface material for corner and or edge degradation mitigation

Method of forming an electronic package

An integrated circuit (IC) device carrier, such as a chip carrier, die carrier, or the like, includes a contact that locally reduces laminate strain within the IC device carrier. One type of contact pad described includes tapered sidewall(s). For example, a positively tapered contact pad includes one or more sidewalls obtusely angled relative to the contact surface of the IC carrier and a negatively tapered contact pad includes one or more sidewalls acutely angled relative to the contact surface of the IC carrier. Another type of contact pad described includes a contact pad connected to one or more pillars. The pillar(s) are also connected to a ring formed within an internal wiring level of the IC device carrier.

Reduction of laminate failure in integrated circuit (IC) device carrier

An electronic package includes a carrier and a semiconductor chip. In a first aspect, a lid is attached to the chip and subsequently the gap between the lid and the carrier is filled by a seal band that includes seal band material and a plurality of shim members. In another aspect, an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material. In another aspect, the lid includes a plurality of surfaces at different topographies to reduce the thickness of the seal band between the topographic lid and the carrier. In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness.

Lid attach optimization to limit electronic package warpage

A laminate includes a plurality of buildup layers disposed on a core and a plurality of unit cells defined in the buildup layers. Each unit cell includes: at least one test via that passes through at least two of the buildup layers and that is electrically connected to testing locations on a probe accessible location of the laminate; and two or more dummy vias disposed in the unit cell. The dummy vias are arranged in the unit cell at one of a plurality of distances from the test via.

Test cell for laminate and method

An electronic package includes a carrier and a semiconductor chip. In a first aspect an interleaved seal band includes a pattern of a first type of seal band material and a second type of seal band material.

In yet another aspect the electronic package further includes a frame concentric with the chip. The lid is attached to the frame with a solder, epoxy or elastomer and placed on the chip with a thermal interface material. The seal band material is dispensed on the chip carrier and the frame is then moved towards the chip carrier allowing a minimum seal band thickness.

Growing community of inventors

Wappingers Falls, NY, United States of America

Sushumna Iruvanti