Xilinx, Inc.

Intel Corporation

Jds Uniphase Corporation

Xilinix, Inc.

Advanced Micro Devices Corporation

Suresh Ramalingam

Gamal Refai-Ahmed

Jaspreet Singh Gandhi

Woon-Seong Kwon

Henley Liu

Tien-Yu Lee

Venkatesan Murali

Douglas E Crafts

Ivor G Barber

Brian Philofsky

Anthony Torza

Chi-Yi Chao

Mohsen Hossein Mardi

Hong Shi

Cheang-Whang Chang

James F Farrell

Duane Cook

Hoa Lap Do

Nagesh K Vodrahalli

Kenzo Ishida

Mark Brian Farrelly

Yohan Usthavia Frans

Ravi V Mahajan

Volker Aue

Mayank Raj

Paul Y Wu

Myongseob Kim

David M Mahoney

Li-Sheng Weng

Steven M Swain

Chuan Xie

Mun Leong Loke

David J Chapman

Siow Chek Tan

Gamal Refai-ahmed

Michael J Costello

Ferdinand F Fernandez

Martin L Voogel

Kun-Yung Chang

James Karp

Paul Winer

Jyoti Kiron Bhardwaj

Richard H Livengood

Boon Yong Ang

Inderjit Singh

Namhoon Kim

Brendan Farley

Nui Chong

Kerry M Pierce

Hong-Tsz Pan

Robert Brainard

Suresh Parameswaran

David J Dougherty

Siegfried B Fleischer

William Edward Allaire

Sanjay M Thekdi

Hiroaki Yamada

Zi-Wen Dong

Raymond E Anderson

Anantharaman Vaidyanathan

Brett Matthew Zaborsky

Thomas Nguyen

Hui-Wen Lin

Nael Zohni

Toshiyuki Hisamura

Dong Wook Kim

Ho Hyung Lee

David K Nakamoto

Joong-Ho Kim

Yingchao Yan

Niranjan Gopinathan

Erik W Egan

Sarajuddin Niazi

Scott McCann

Hoa Do

Aslam Yehia

Md Malekkul Islam

Arun Kumar Varadarajan Rajagopal

Ken Chang

Huayan Wang

Yu Hsiang Sun

Nagadeven Karunakaran

Jonathan Chang

Daniel Elftmann

Myung-June Lee

Manoj Nachnani

Lik Tsang

Jens Weis

Dennis CP Leung

A chip package and methods for fabricating the same are provided that include integrated devices embedded and coupled in series between a lower surface of a package substrate and an integrated circuit die of the chip package. In some examples, the integrated devices are disposed side by side embedded in a common package substrate. In other examples, one of the series coupled integrated devices is embedded in a first package substrate while another of the series coupled integrated devices is embedded in a second package substrate that is stacked directly in contact with the first package substrate. The integrated devices may be passive and/or active integrated devices.

Chip package with core embedded integrated devices

An electronic device having a frame for coupling a plurality of thermal management devices to the printed circuit board is provided. The electronic device includes a first chip package mounted to the PCB and a second chip package mounted to the PCB. The frame is secured to the PCB, and the frame has a first aperture disposed over the first chip package and a second aperture disposed over the second chip package. The plurality of thermal management devices coupled to the frame includes a first thermal management device contacting an IC die of the first chip package through the first aperture and a second thermal management device contacting an IC die of the second chip package through the second aperture.

Frame for coupling of a thermal management device to a printed circuit board

Disclosed herein is a heat spreader for use with an IC package, the heat spreader having features for enhanced temperature control of the IC package. A heat spreader for use with an IC package is disclosed. In one example, the heat spreader includes a metal body that has a sealed internal cavity. A thermally conductive material fills the sealed internal cavity. The thermally conductive material has an interstitial space sufficient to allow fluid to pass therethrough. A first phase change material fills at least a portion of the interstitial space of the thermally conductive material.

Heat spreader for a semiconductor package

A chip package and method for fabricating the same are provided that includes a near-die integrated passive device. The near-die integrated passive device is disposed between a package substrate and an integrated circuit die of a chip package. Some non-exhaustive examples of an integrated passive device that may be disposed between the package substrate and the integrated circuit die include a resistor, a capacitor, an inductor, a coil, a balum, or an impedance matching element, among others.

Chip package with near-die integrated passive device

A chip package assembly and method for fabricating the same are provided which utilize a plurality of posts in mold compound for improved resistance to delamination. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die, a substrate, a redistribution layer, a mold compound and a plurality of posts. The redistribution layer provides electrical connections between circuitry of the first IC die and circuitry of the substrate. The mold compound is disposed in contact with the first IC die and spaced from the substrate by the redistribution layer. The plurality of posts are disposed in the mold compound and are laterally spaced from the first IC die. The plurality of posts are not electrically connected to the circuitry of the first IC die.

Fanout integration for stacked silicon package assembly

Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path.

Heterogeneous integration module comprising thermal management apparatus

An antenna assembly is provided having passive cooling elements that enable compact design. In one example, an antenna assembly is provided that includes a heat sink assembly having an interior side and an exterior side, an antenna array, an antenna circuit board, and a radome. The antenna circuit board includes at least one integrated circuit (IC) die. The IC die has a conductive primary heat dissipation path to the interior side of the heat sink assembly. The radome is coupled to the heat sink assembly and encloses the antenna circuit board and the antenna array between the radome and the heat sink assembly. The heat sink assembly includes a metal base plate and at least a first heat pipe embedded with the metal base plate. The first heat pipe is disposed between the metal base plate and the IC die.

Radome with integrated passive cooling

A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.

Stacked silicon package assembly having vertical thermal management

In one example, a method includes providing a first side of a semiconductor substrate with a plurality of transistors, etching a second side of the substrate, opposite the first side, with a pattern of trenches, the trenches having a pre-defined depth and width, and providing the etched semiconductor substrate in a package. In one example, the predefined depth and width of the trenches is such so as to increase the surface area of the second side of the substrate by at least 20 percent. In one example, the method also includes providing a layer of a thermal interface material (TIM) on the second side of the substrate, including to fill at least a portion of the trenches.

Thermal enablement of dies with impurity gettering

A heat exchanger and an antenna assembly having the same are described herein that enable a compact antenna design with good thermal management. In one example, a heat exchanger is provided that includes tube-shaped body. A main cooling volume is formed between the top and bottom surfaces proximate to the outside wall. The main cooling volume has an inlet formed through the top surface and an outlet formed through the bottom surface. A return volume is formed adjacent the inside diameter wall and is circumscribed by the main cooling volume. The return volume has an outlet formed through the top surface and an inlet formed through the bottom surface. One or more exterior fins are coupled to an exterior side of the outside wall. A plurality of fins extend into the main cooling volume. A plurality of inner fins extend into a passage from the inside diameter wall.

Remote active cooling heat exchanger and antenna system with the same

A chip package assembly and method of fabricating the same are described herein. The chip package assembly generally includes at least one integrated circuit (IC) die that has had the original solder interconnects at least partially replaced to enhance the reliability of a redistribution layer disposed between the IC die and the substrate. In the resulting chip package assembly, at least one IC die includes first and second pillars extending from exposed contact pads through a first mold compound. The second pillars are fabricated from a material that has a composition different than that of the first pillars. A redistribution layer is formed on the first and second pillars. The solder interconnects mechanically couple the redistribution layer to landing pads of a substrate. The solder interconnects also electrically couple circuitry of the substrate to the circuitry of the IC die through the redistribution layer and first and second pillars.

Package integration for laterally mounted IC dies with dissimilar solder interconnects

A cooling plate assembly and electronic device having the same are provided which utilize active and passive cooling devices for improved thermal management of one or more chip package assemblies included in the electronic device. In one example, a cooling plate assembly is provided that includes a cooling plate having a first surface and an opposing second surface, a first active cooling device coupled to the first surface of the cooling plate, and a first passive cooling device coupled to the second surface of the cooling plate.

Thermal heat spreader plate for electronic device

A chip package assembly and method for fabricating the same are provided which utilize a plurality of extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a first integrated circuit (IC) die mounted to a substrate, a cover disposed over the first IC die, and a plurality of extra-die conductive posts disposed between the cover and substrate. The extra-die conductive posts provide a heat transfer path between the cover and substrate that is laterally outward of the first IC die.

Stacked silicon package assembly having thermal management

An electronic device is provided that balances the force applied to temperature control elements such that stress within components of the electronic device can be effectively managed. In one example, an electronic device is provided that includes a printed circuit board (PCB), a chip package, a thermal management system, a thermal spreader, and first and second biasing members. The chip package is mounted to the PCB. The thermal management system and spreader are disposed the opposite of the chip package relative to the PCB. The first biasing member is configured to control a first force sandwiching the chip package between the thermal spreader and the PCB. The second biasing member is configured to control a second force applied by the thermal management system against the thermal spreader. The first force can be adjusted separately from the second force so that total forces applied to the chip package and PCB may be effectively balanced.

Force balanced package mounting

Some examples described herein provide for three-dimensional (3D) thermal management apparatuses for thermal energy dissipation of thermal energy generated by an electronic device. In an example, an apparatus includes a thermal management apparatus that includes a primary base, a passive two-phase flow thermal carrier, and fins. The thermal carrier has a carrier base and one or more sidewalls extending from the carrier base. The carrier base and the one or more sidewalls are a single integral piece. The primary base is attached to the thermal carrier. The carrier base has an exterior surface that at least a portion of which defines a die contact region. The thermal carrier has an internal volume aligned with the die contact region. A fluid is disposed in the internal volume. The fins are attached to and extend from the one or more sidewalls of the thermal carrier.

Three-dimensional thermal management apparatuses for electronic devices

Growing community of inventors

Fremont, CA, United States of America

Suresh Ramalingam