Texas Instruments Corporation

Sunil V Hattangady

Rajesh B Khamankar

George R Misium

Hiroaki Niimi

Douglas Ticknor Grider

Robert M Wallace

Glen D Wilk

Robert Kraft

Yi Wei

Ming J Hwang

Che-Jen Hu

Jaideep Mavoori

Paul Tiner

Mark Stephen Rodder

James Joseph Chambers

Antonio L P Rotondaro

Srikanth Krishnan

Thomas C Holloway

Yasutoshi Okuno

John W Kuehne

Tad (Douglas) Grider

A method of fabricating a transistor includes providing a semiconductor substrate having a surface and forming a nitride layer outwardly of the surface of the substrate. The nitride layer is oxidized to form a nitrided silicon oxide layer comprising an oxide layer beneath the nitride layer. A high-K layer is deposited outwardly of the nitride layer, and a conductive layer is formed outwardly of the high-K layer. The conductive layer, the high-K layer, and the nitrided silicon oxide layer are etched and patterned to form a gate stack. Sidewall spacers are formed outwardly of the semiconductor substrate adjacent to the gate stack, and source/drain regions are formed in the semiconductor substrate adjacent to the sidewall spacers.

Semiconductor with a nitrided silicon gate oxide and method

Method for annealing ultra-thin, high quality gate oxide layers using oxidizer/hydrogen mixtures

Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile

A method of forming an ultra-thin dielectric layer, including the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density.

Method for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates

A method of forming an ultra-thin gate oxide ( ) for a field effect transistor ( ). The gate oxide ( ) is formed by combining an oxidizing agent (e.g., N O, CO ) with an etching agent (e.g., H ) and adjusting the partial pressures to controllably grow a thin (&tilde;12 Angstroms) high quality oxide ( ).

Controllable oxidation technique for the formation of high-quality ultra-thin gate oxide using carbon dioxide as the oxidizing agent

A method of making a semiconductor device and the device. The device, according to a first embodiment, is fabricated by providing a silicon ( ) surface, forming on the surface a dielectric layer of crystalline silicon nitride and forming an electrode layer on the dielectric layer of silicon nitride. The silicon ( ) surface is cleaned and made atomically flat. The dielectric layer if formed of crystalline silicon nitride by placing the surface in an ammonia ambient at a pressure of from about 1&times;10 to about 1&times;10 Torr at a temperature of from about 850&deg; C. to about 1000&deg; C. The electrode layer is heavily doped silicon. According to a second embodiment, there is provided a silicon ( ) surface on which is formed a first dielectric layer of crystalline silicon nitride having a thickness of about 2 monolayers. A second dielectric layer compatible with silicon nitride and having a higher dielectric constant than silicon nitride is formed on the first dielectric layer and an electrode layer is formed over the second dielectric layer. A third dielectric layer of silicon nitride having a thickness of about 2 monolayers can be formed between the second dielectric layer and the electrode layer. The second dielectric layer is preferably taken from the class consisting of tantalum pentoxide, titanium dioxide and a perovskite material. Both silicon nitride layers can be formed as in the first embodiment. The electrode layer is preferably heavily doped silicon

Process to produce ultrathin crystalline silicon nitride on Si (111) for advanced gate dielectrics

A method of fabricating a semiconductor MOS device and the device wherein there is initially provided a semiconductor substrate having a gate insulator layer thereon and intimate therewith. A region of one of a nitride or oxynitride is formed at the surface region of the layer remote from the substrate having sufficient nitride to act as a barrier against the migration of dopant therethrough to the substrate. A doped polysilicon gate or a metal gate is then formed over the region of a nitride or oxynitride. The amount of nitride in the insulator layer intimate and closely adjacent to the substrate is insufficient to materially alter the characteristics of the device being fabricated. The substrate is preferably silicon, the oxide and nitride are preferably those of silicon and the dopant preferably includes boron. The step of forming a region of one of a nitride or oxynitride includes the step of injecting neutral atomic nitrogen into the surface of the gate insulator layer surface remote from the substrate. The region of one of a nitride or oxynitride is from about 1 to about 2 monolayers.

Fabrication technique for controlled incorporation of nitrogen in gate dielectric

Controllable oxidation technique for high quality ultrathin gate oxide formation

A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (,) on a wafer (,) surface, exposing the surface of the oxide layer (,) to a nitrogen ion containing plasma to form a nitrided layer (,). Next, a photoresist layer (,) is deposited over a portion of the oxide layer (,) and the isolation (,), followed by etching of the exposed nitrided layer,and a portion of the oxide layer (,) to create a thinner silicon dioxide layer (,). The photoresist layer (,) is removed, the wafer (,) is cleaned and then the thinner silicon dioxide layer (,) is removed prior to a final oxidation step to form a thinner silicon dioxide layer (,) having a different thickness than the silicon dioxide layer (,).

Nitridation for split gate multiple voltage devices

An embodiment of the instant invention is a method of fabricating an electronic device over a semiconductor substrate which includes a dielectric layer formed between a first structure and a second structure, the method comprising the steps of: growing an oxide-containing layer (layer,of FIGS.,) on the first structure (substrate,of FIGS.,); forming a silicon-containing layer (layer,of FIG.,) on the oxide-containing layer; oxidizing substantially all of the silicon-containing layer by subjecting it to an ambient comprised of oxygen and nitrogen with a substrate temperature around 700 to 800 C.; and forming the second structure (layer,of FIG.,) on the oxidized silicon-containing layer. Preferably, the step of oxidizing substantially all of the silicon-containing layer is performed by subjecting the silicon-containing layer to an ambient containing: N,O with a wafer temperature around 700 to 800 C.; or NO with a wafer temperature around 700 to 800 C. The nitrogen is, preferably, incorporated between the oxide-containing layer and the first structure and/or between the oxide-containing layer and the oxidized silicon-containing layer.

Stacked/composite gate dielectric which incorporates nitrogen at an interface

A method of making a semiconductor device and the device. The device, according to a first embodiment, is fabricated by providing a silicon (111) surface, forming on the surface a dielectric layer of crystalline silicon nitride and forming an electrode layer on the dielectric layer of silicon nitride. The silicon (111) surface is cleaned and made atomically flat. The dielectric layer if formed of crystalline silicon nitride by placing the surface in an ammonia ambient at a pressure of from about 1&times;10,to about 1&times;10,Torr at a temperature of from about 850&deg; C. to about 1000&deg; C. The electrode layer is heavily doped silicon. According to a second embodiment, there is provided a silicon (111) surface on which is formed a first dielectric layer of crystalline silicon nitride having a thickness of about 2 monolayers. A second dielectric layer compatible with silicon nitride and having a higher dielectric constant than silicon nitride is formed on the first dielectric layer and an electrode layer is formed over the second dielectric layer. A third dielectric layer of silicon nitride having a thickness of about 2 monolayers can be formed between the second dielectric layer and the electrode layer. The second dielectric layer is preferably taken from the class consisting of tantalum pentoxide, titanium dioxide and a perovskite material. Both silicon nitride layers can be formed as in the first embodiment.

Process to produce ultrathin crystalline silicon nitride on Si(111) for advanced gate dielectrics

A method is disclosed for making gate oxides on a silicon wafer surface for multiple voltage applications comprising the steps of growing an oxide layer (,) on a wafer (,) surface. Next, a photoresist layer (,) is deposited over a portion of the oxide layer (,) and the isolation (,). The entire wafer (,) is exposed to a nitrogen ion containing plasma to form a nitrided layer (,). The photoresist (,) is removed, and the exposed portion of the oxide layer (,) is etched to the wafer (,) surface. Finally, an oxidation step forms a silicon dioxide layer (,) having a different thickness than the silicon dioxide layer (,).

Low temperature process for multiple voltage devices

A method is disclosed of nitridating an oxide containing surface the disclosed method includes the steps of, obtaining a substrate, growing an oxide layer on the substrate, exposing the surface of the oxide layer to a nitrogen ion containing plasma at, e.g., room temperature, wherein the nitrogen ions form a nitrided layer on the oxide layer resistant to chemistries used to etch oxide.

Remote plasma nitridation to allow selectively etching of oxide

A gate stack (,) including a gate dielectric with reduced effective electrical thickness. A high-k dielectric (,) is formed over the silicon substrate (,). Remote plasma nitridation of the high-k dielectric is performed to create a nitride layer (,) over the high-k dielectric (,). A conductive layer (,) is formed over the nitride layer (,) forming the gate electrode.

Growing community of inventors

McKinney, TX, United States of America

Sunil V Hattangady