Samsung Electronics Co., Ltd.

Sungho Jang

Jinseob Kim

Yoosang Hwang

Wookrae Kim

Jinyong Kim

Daehoon Han

Bong-Soo Kim

Kiseok Lee

Jiyoung Kim

Keunnam Kim

Joon Soo Han

Chan-Sic Yoon

Jemin Park

Kang-Uk Kim

Dongoh Kim

Jungchul Lee

Augustin Jinwoo Hong

Jaehwang Jung

Garam Choi

Minhwan Seo

Hoin Lee

Hyuck Shin

Kiwook Jung

Kwang Soo Kim

Dongjin Lee

Dong Jin Lee

Sungyeol Kim

Tae-Hyun Kim

Youngjoo Lee

Jungmin Ko

Kyunghyun Kim

Seungwoo Lee

Daeik Kim

Younghwan Kim

Hanjin Lim

Junhee Lim

Myungjun Lee

Youngdo Kim

Injae Lee

Sang Ki Nam

Kyung-Eun Kim

Keunhee Bai

Ilgweon Kim

Junbum Park

Sangki Nam

Kyoungmin Kim

Hyoungsub Kim

Seungkoo Lee

Jongsu Kim

Sangwoo Bae

Yoonjae Kim

Nam Kyun Kim

Byeonghwan Jeon

Gwangsik Park

Kuihyun Yoon

Kangmin Jeon

Ho-Kyun An

Insang Jeon

Seokjae Lee

Bokyeon Won

Daewon Kang

Akinori Okubo

Wondon Joo

Won-Kyung Park

Badro Im

Nakjin Son

Kwonsang Seo

Kul Inn

Chansoo Kang

Youngkyu Park

Jihye Hwang

Youngkuk Kim

Yoojin Jeong

Donghyub Lee

Dong-Hyub Lee

Kyungsik Kang

Youngduk Suh

Changsoon Lim

Jonghun Pi

Jiyoung Chu

Chan Min Lee

Jeong-Gil Kim

Seunghan Baek

Jangwoon Sung

Janghwi Lee

Sangjoon Hong

Jaehyun Yeo

Taesung Kang

Youngkyu Lee

Yozo Matsuda

Hochul Kim

Kyunjin Lee

Jungmo Yang

Seungbin Ahn

Changheon Lee

Younguk Jin

Juyeon Jang

A plasma confinement ring includes a lower ring, an upper ring on the lower ring, and a connection ring extended to connect the lower ring to the upper ring. The lower ring includes a lower center hole vertically penetrating the lower ring at a center of the lower ring and at least one slit penetrating the lower ring in a region outside the lower center hole. The slit is structured to pass a more amount of air or gas at a first portion closer to the center of the lower ring than at a second portion farther from the center of the lower ring.

Plasma confinement ring, semiconductor manufacturing apparatus including the same, and method of manufacturing a semiconductor device using the same

A semiconductor measurement apparatus includes an illumination unit including a light source and at least one illumination polarization element, a light receiving unit including at least one light-receiving polarization element disposed on a path of light reflected by a sample, and an image sensor positioned to receive light passing through the at least one light-receiving polarization element and configured to output an original image, and a control unit configured to determine, by processing the original image, a selected critical dimension among critical dimensions of a structure included in a region of the sample. The control unit is configured to obtain a plurality of sample images by selecting regions of the original image in which a peak due to interference appears, to determine a plurality of elements included in a Mueller matrix using the plurality of sample images, and to determine the selected critical dimension based on the plurality of elements.

Semiconductor measurement apparatus

An apparatus includes first and second VI sensors, an optical sensor, and an arcing detector. The first VI sensor is disposed in a power filter or on a power supply line connected to a heater disposed in a lower electrode of a process chamber in which a plasma process is performed. The first VI sensor senses a harmonic generated from a first power supply supplying power to the lower electrode and outputs a first signal. The optical sensor senses an intensity of light generated from the process chamber and outputs a second signal. The second VI sensor is disposed on a power supply line connected to an upper electrode and senses a harmonic generated from a second power supply supplying power to the upper electrode and outputs a third signal. The arcing detector determines whether arcing occurs based on one or more of the first, second, and third signals.

Apparatus for arcing diagnosis, plasma process equipment including the same, and arcing diagnosis method

A semiconductor measurement apparatus may include an illumination unit configured to irradiate light to the sample, an image sensor configured to receive light reflected from the sample and output multiple interference images representing interference patterns of polarization components of light, an optical unit in a path through which the image sensor receives light and including an objective lens above the sample, and a control unit configured to obtain, by processing the multi-interference image, measurement parameters determined from the polarization components at each of a plurality of azimuth angles defined on a plane perpendicular to a path of light incident to the image sensor. The control unit may be configured to determine a selected critical dimension to be measured from a structure in the sample based on measurement parameters. The illumination unit and/or the optical unit may include a polarizer and a compensator having a ¼ wave plate.

A semiconductor measurement device may include an illumination apparatus having a polarizer on a propagation path of light output from a light source; an optical assembly including an objective lens configured to allow light passing through the polarizer to be incident on a sample and a beam splitter configured to transmit light reflected from the sample to first and second sensors; and a controller. The controller may be configured to determine an alignment state of patterns in a first region of the sample using a first original image output by the first sensor and an alignment state of patterns in a second region of the sample using a second original image output by the second sensor. The first sensor includes a first image sensor and a self-interference generator in a path along which light is incident on the first image sensor. The second sensor includes a second image sensor.

Provided are a level sensor configured to detect a height level of a substrate, and a substrate processing apparatus including the level sensor. The level sensor includes a measurement light source configured to radiate measurement light toward the substrate, a prism configured to split reflected light of the measurement light into first polarized light and second polarized light and generate a first optical path length difference between the first polarized light and the second polarized light, an optical path length modulator configured to keep constant an optical path length of the first polarized light and periodically change an optical path length of the second polarized light, and a detector configured to detect the first optical path length difference based on an interference signal between the first polarized light and the second polarized light.

Level sensor and substrate processing apparatus including the same

Provided is a hyperspectral imaging (HSI) apparatus. The HSI apparatus includes: a first slit plate configured to introduce an output beam; a first aspherical mirror configured to reflect the introduced output beam; a first grating having a planar reflective surface, the first grating configured to generate a plurality of first split beams by splitting the output beam after being reflected by the first aspherical mirror; and a first camera configured to detect the plurality of first split beams.

Hyperspectral imaging (HSI) apparatus and inspection apparatus including the same

An extreme ultraviolet (EUV) collector inspection apparatus and method capable of precisely inspecting a contamination state of an EUV collector and EUV reflectance in accordance with the contamination state are provided. The EUV collector inspection apparatus includes a light source arranged in front of an EUV collector to be inspected and configured to output light in a visible light (VIS) band from UV rays, an optical device configured to output narrowband light from the light, and a camera configured to perform imaging from an UV band to a VIS band. An image by wavelength of the EUV collector is obtained by using the optical device and the camera and a contamination state of the EUV collector is inspected.

Extreme ultraviolet (EUV) collector inspection apparatus and method

A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

Semiconductor memory device

A method of manufacturing a semiconductor includes generating plasma in an amplifying tube using gas as a gain medium; detecting a state of the plasma generated in the amplifying tube; determining a virtual laser gain based on the detected state of the plasma; controlling the state of the plasma such that the virtual laser gain is within a target range; and manufacturing the semiconductor device including performing an exposure process on a substrate using a laser beam output from the amplifying tube adjusted to have the virtual laser gain within the target range.

Method of exposure using extreme ultraviolet and method of manufacturing a semiconductor device using the same

An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of a sensing bit line and a complementary sensing bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor; and a first offset canceling unit connecting the bit line to the complementary sensing bit line in response to an offset canceling signal, and including a first offset canceling transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset canceling transistor shares a common impurity region with the first NMOS transistor.

Integrated circuit devices

An extreme ultraviolet exposure system includes an exposure chamber having an internal space, upper and lower electrostatic chucks, a power supply, a light source, and a mask. The upper electrostatic chuck includes first and second electrodes that are adjacent to one another and that generate an electric field of different polarities, respectively, to provide an electrostatic force. The mask is attachable to the lower surface of the upper electrostatic chuck by the electrostatic force. The mask has a metal thin film pattern including a first region in which a metal thin film that shields the electric field, and a second region in which the metal thin film is not disposed and through which the electric field is transmitted. When the mask is attached, the electric field transmitted through the second region applies an attractive force or a repulsive force to charged particles in the exposure chamber.

Extreme ultraviolet exposure system

An optical emission spectroscopy (OES) calibration system includes a chamber, an adapter, an OES device, a calibration device, and a spectrometer. The chamber includes a viewport. The adapter is fastened to the viewport, and includes a first beam splitter and a second beam splitter. The OES device detects plasma light generated in the chamber and transmitted through the adapter and generates OES data based on the detected plasma light. The calibration device includes a light source, and generates correction data for compensating for deviations in the OES data. The spectrometer detects light emitted from the light source and split by the first beam splitter or the second beam splitter. Each of the OES device, the calibration device, and the spectrometer is fastened to the adapter through an optical cable, and the calibration device generates the correction data using an intensity of light detected by the spectrometer.

Optical emission spectroscopy calibration device and system including the same

Disclosed are an apparatus for and a method of performing an inspection and metrology process. The apparatus may include a stage configured to load a substrate thereon, a sensor on the stage, an object lens between the sensor and the stage, a light source generating an illumination light to be transmitted to the substrate through the object lens, a first band filtering part between the light source and the object lens to control a wavelength of the illumination light within a first bandwidth, and a second band filtering part between the light source and the object lens to control a wavelength of the illumination light within a second bandwidth, which is smaller than the first bandwidth.

Apparatus for and method of performing inspection and metrology process

Semiconductor memory device and method of manufacturing the same

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Seoul, South Korea

Sungho Jang