Freescale Semiconductor,inc.

Nxp Usa, Inc.

Sung-Taeg Kang

Cheong Min Hong

Jane A Yater

Brian A Winstead

Asanga H Perera

Konstantin V Loiko

Gowrishankar L Chindalore

Marc A Rossow

Ko-Min Chang

Byoung W Min

Jacob Williams

Rode R Mora

David G Kolar

Jinmiao James Shen

Taras A Kirichenko

ShanShan Du

Mehul D Shroff

Ramachandran Muralidhar

Robert F Steimle

Rajesh A Rao

Ronald J Syzdek

Matthew Thomas Herrick

Horacio P Gasquet

Spencer E Williams

Euhngi Lee

A method of forming a split gate memory cell structure using a substrate includes forming a gate stack comprising a select gate and a dielectric portion overlying the select gate. A charge storage layer is formed over the substrate including over the gate stack. A first sidewall spacer of conductive material is formed along a first sidewall of the gate stack extending past a top of the select gate. A second sidewall spacer of dielectric material is formed along the first sidewall on the first sidewall spacer. A portion of the first sidewall spacer is silicided using the second sidewall spacer as a mask whereby silicide does not extend to the charge storage layer.

Methods and structures for a split gate memory cell structure

A split gate memory array includes a first row having memory cells; a second row having memory cells, wherein the second row is adjacent to the first row; and a plurality of segments. Each segment includes a first plurality of memory cells of the first row, a second plurality of memory cells of the second row, a first control gate portion which forms a control gate of each memory cell of the first plurality of memory cells, and a second control gate portion which forms a control gate of each memory cell of the second plurality of memory cells. The first control gate portion and the second control gate portion converge to a single control gate portion between neighboring segments of the plurality of segments.

Scalable split gate memory cell array

A method of forming a flash memory cell includes forming a first hard mask and a second hard mask on a substrate. A select gate is formed as a spacer around the first hard mask. A charge storage layer is formed over the first and second hard masks and the select gate. A control gate is formed as a spacer around the second hard mask. A recess in the control gate is filled with a dielectric material. The recess is formed between a curved sidewall of the control gate and a sidewall of the charge storage layer directly adjacent the curved sidewall of the control gate.

Non-volatile memory (NVM) cell and a method of making

A method and apparatus are described for integrating high voltage (HV) transistor devices and medium voltage or dual gate oxide (DGO) transistor devices with low voltage (LV) core transistor devices on a single substrate, where each high voltage transistor device () includes a metal gate (), an upper high-k gate dielectric layer (), a middle gate dielectric layer () formed with a relatively lower high-k dual gate oxide layer, and a lower high voltage gate dielectric stack () formed with one or more low-k gate oxide layers (), where each DGO transistor device () includes a metal gate (), an upper high-k gate dielectric layer (), and a middle gate dielectric layer () formed with a relatively lower high-k dual gate oxide layer, and where each core transistor device () includes a metal gate (), an upper high-k gate dielectric layer (), and a base oxide layer () formed with one or more low-k gate oxide layers.

Method of forming different voltage devices with high-k metal gate

Methods for fabricating dense arrays of electrically conductive nanocrystals that are self-aligned in depressions at target locations on a substrate, and semiconductor devices configured with nanocrystals situated within a gate stack as a charge storage area for a nonvolatile memory (NVM) device, are provided.

Method to form self-aligned high density nanocrystals

Methods and related structures are disclosed for forming contact landing regions in split-gate NVM (non-volatile memory) systems. A dummy select gate structure is formed while also forming select gates for split-gate NVM cells. A control gate layer is formed over the select gates and the dummy select gate structure, as well as an intervening charge storage layer. The control gate material will fill in gaps between the select gate material and the dummy select gate material. A non-patterned spacer etch is then used to etch the control gate layer to form a contact landing region associated with the dummy select gate structure while also forming spacer control gates for the split-gate NVM cells. The disclosed embodiments provide improved (e.g., more planar) contact landing regions without requiring additional processing steps and without increasing the pitch of the resulting NVM cell array.

Methods for forming contact landing regions in split-gate non-volatile memory (NVM) cell arrays

A method of making a semiconductor device includes forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the memory gate structure comprises a first gate separated from a second gate by a charge storage layer. A logic gate structure is formed in a logic region of the semiconductor device. A hard mask is formed over at least the metal electrode portion. The nonvolatile memory region is selectively etched such that a first recess is formed in the first gate and a second recess is formed in the second gate.

Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor

A process integration is disclosed for fabricating non-volatile memory (NVM) cells (--) on a first flash cell substrate area () which are encapsulated in one or more planar dielectric layers () prior to forming an elevated substrate () on a second CMOS transistor area () on which high-k metal gate electrodes (--) are formed using a gate-last HKMG CMOS process flow without interfering with the operation or reliability of the NVM cells.

Method to form a polysilicon nanocrystal thin film storage bitcell within a high k metal gate platform technology using a gate last process to form transistor gates

A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A control gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region. A logic gate structure formed in a logic region has a metal work function surrounded by an insulating layer.

Integrated split gate non-volatile memory cell and logic device

Non-volatile memory (NVM) cell

Split-gate non-volatile memory (NVM) cells having select-gate sidewall metal silicide regions are disclosed along with related manufacturing methods. Spacer etch processing steps are used to expose sidewall portions of select gates. Metal silicide regions are then formed within these sidewall portions of the select gates. Further, metal silicide regions can also be formed in top portions of the select gates. Further, the select gates can also be formed with one or more notches. By expanding the size of the metal silicide region to include the sidewall portion of the select gate, the select gate wordline (e.g., polysilicon) resistance is reduced for split-gate NVM arrays, the electrical contact to the select gate is improved, and performance of the select-gate NVN cell is improved.

Split-gate memory cells having select-gate sidewall metal silicide regions and related manufacturing methods

Method of forming different voltage devices with high-K metal gate

A method of making a semiconductor structure includes forming a select gate over a substrate in an NVM portion and a first protection layer over a logic portion. A control gate and a storage layer are formed over the substrate in the NVM portion, wherein the control and select gates have coplanar top surfaces. The charge storage layer is under the control gate, along adjacent sidewalls of the select gate and control gate, and is partially over the top surface of the select gate. A second protection layer is formed over the NVM portion and the logic portion. The second protection layer and the first protection layer are removed from the logic portion leaving a portion of the second protection layer over the control gate and the select gate. A gate structure is formed over the logic portion comprising a high k dielectric and a metal gate.

Non-volatile memory (NVM) and high-k and metal gate integration using gate-first methodology

A split gate memory structure includes a pillar of active region having a first source/drain region disposed at a first end of the pillar, a second source/drain region disposed at a second end of the pillar, opposite the first end, and a channel region between the first and second source/drain regions. The pillar has a major surface extending between first and the second ends which exposes the first source/drain region, the channel region, and the second source/drain region. A select gate is adjacent the first source/drain region and a first portion of the channel region, wherein the select gate encircles the major surface the pillar. A charge storage layer is adjacent the second source/drain region and a second portion of the channel region, wherein the charge storage layer encircles the major surface the pillar. A control gate is adjacent the charge storage layer, wherein the control gate encircles the pillar.

Growing community of inventors

Austin, TX, United States of America

Sung-Taeg Kang