National Semiconductor Corporation

Sharp Kabushiki Kaisha Corporation

Sung T Ahn

Sheldon Aronowitz

Courtney L Hart

Katsuji Iguchi

Seizo Kakimoto

John M Pierce

Shigeki Hayashida

A method for preparing a semiconductor device comprises the following steps: (I) depositing at least nitride film on the whole surface of a semiconductor substrate having a field oxide film, (II) removing a portion of the nitride film from a gate-formation region to form an opening at the nitride film up to the substrate, (III) thereafter forming by selective oxidation a vertically projecting oxide film on the substrate at the opening portion, (IV) then removing all the films including the oxide film and the nitride film each covering the substrate to form a dug part of the substrate at the gate formation region, (V) providing on the dug part a gate oxide film and a gate electrode in the order, (VI) doping an impurity ion into the substrate in a manner of self-alignment using the gate electrode as a mask, and (VII) applying heat treatment to the substrate to form an impurity-diffused region.

Method for controlling gate size for semiconduction process

A method of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.

Application of electronic properties of germanium to inhibit n-type or

A structure of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.

A method of fabricating an insulating gate type field-effect transistor in which a region having a low carrier density for mitigating electric field is provided so as to abut on a source/drain region having a high carrier density, the method comprising the steps of: forming a gate insulating film and a gate electrode on a semiconductor substrate; depositing an insulating thin film on the gate electrode and the gate insulating film to a vertical thickness; and performing from above the insulating thin film, ion implantation at an implantation energy inducing a projected range of ions approximately equal to the vertical thickness of the insulating thin film so as to form the source/drain region; wherein a horizontal thickness of the insulating thin film on opposite sides of the gate electrode is larger than a sum of a lateral diffusion distance of the source/drain region at the time of the ion implantation and a lateral diffusion distance of the source/drain region after the ion implantation.

Method of fabricating semiconductor element having lightly doped drain

Application of electronic properties of germanium to inhibit N-type or

An integrated circuit device is fabricated upon a semiconductor wafer by first forming a stop layer upon the surface of the wafer. Holes are formed through the stop layer and wells are formed in the semiconductor material of the semiconductor wafer below the openings. A dielectric layer is formed over the the surface of the device substantially filling the wells and covering the stop layer. The dielectric layer is then planarized to substantially the level of the stop layer. A PAD oxide layer is provided between the stop layer and the surface of the semiconductor device. Conventional thin film oxidation of the wells and implants into the side walls of the wells are performed. An abrasive mechanical polisher is used to perform the planarization wherein the mechanical polisher is provided with the self-stopping feature when it encounters the stop layer.

Growing community of inventors

Nara, Japan

Sung T Ahn