Vanguard International Semiconductor Corporation

Sung-Min Wei

Chih-Cherng Liao

Wen-Tsung Wang

Yi-Tsung Jan

Zhe-Xiong Wu

Yuan-Heng Li

Tung-Chia Ching

Mao-Tsang Chen

Mao-Tsung Chen

A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed on the semiconductor substrate, and a hard mask layer formed on the gate. A first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate equal to half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer and the hard mask layer as masks.

Method for fabricating source/drain devices

A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed thereon, a first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate less than half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer as a mask.

A process for creating a storage node structure, for a DRAM capacitor structure, featuring increased storage node surface area, via use of an HSG silicon layer, on an underlying storage node shape, has been developed. The process features the use of an isotropic, buffered HF etch procedure, applied to the HSG silicon layer, to increase the space between the concave and convex features, of the HSG silicon layer. The increased space between the concave and convex features of the HSG silicon layer, allows a capacitor dielectric layer, of uniform thickness, to be formed on the isotopically etched, HSG silicon layer.

Isotropic etching of a hemispherical grain silicon layer to improve the

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Hsinchu, Taiwan

Sung-Min Wei