Samsung Electronics Co., Ltd.

Sung-min Sim

Dong-Hyeon Jang

Seung-Kwan Ryu

Soon-Bum Kim

Hyun-Soo Chung

Kang-Wook Lee

In-Young Lee

Young-Hee Song

Young-hee Song

Se-Young Jeong

Myeong-Soon Park

Jae-Sik Chung

Ung-Kwang Kim

Keum-Hee Ma

Se-Yong Oh

Se-yong Oh

Hee-Kook Choi

Hwang-kyu Yun

Chan-eon Park

Wan-gyun Choi

Jae-sik Chung

Provided is a method of forming conductors (e.g., metal lines and/or bumps) for semiconductor devices and conductors formed from the same. First and second seed metal layers may be formed. At least one mask may be formed on a portion on which a conductor is to be formed. An exposed portion may be oxidized. The oxidized portion may be removed. A conductive structure may be formed on an upper surface of a portion which is not oxidized. The conductors may be metal lines and/or bumps. The conductive structures may be solder balls.

Method of forming metal lines and bumps for semiconductor devices

A semiconductor chip structure may include a semiconductor chip, a first insulation layer and a redistribution layer. The first insulation layer may be formed on the semiconductor chip. The first insulation layer may have at least one first groove formed at an upper surface portion of the first insulation layer. Further, the at least one first groove may have an upper width and a lower width greater than the upper width. The redistribution layer may be partially formed on the first insulation layer. The redistribution layer may have at least one first protrusion formed on a lower surface portion of the redistribution layer. The first protrusion may have an upper width and a lower width less than the upper width. The first protrusion may be inserted into the at least one first groove.

Semiconductor chip structure, method of manufacturing the semiconductor chip structure, semiconductor chip package, and method of manufacturing the semiconductor chip package

A method of fabricating wafer level chip scale packages may involve forming a hole to penetrate through a chip pad of an IC chip. A base metal layer may be formed on a first face of a wafer to cover inner surfaces of the hole. An electrode metal layer may fill the hole and rise over the chip pad. A second face of the wafer may be grinded such that the electrode metal layer in the hole may be exposed through the second face. By electroplating, a plated bump may be formed on the electrode metal layer exposed through the second face. The base metal layer may be selectively removed to isolate adjacent electrode metal layers. The wafer may be sawed along scribe lanes to separate individual packages from the wafer.

Fabrication method of wafer level chip scale packages

A wafer level chip scale package may have a gap provided between a solder bump and a bump land. The gap may be filled with a gas. A method of manufacturing a wafer level chip scale package may involve forming a redistribution line having a first opening, forming a seed metal layer having a second opening including an undercut portion, and forming the gap using the first and the second openings.

Wafer level chip scale package having a gap and method for manufacturing the same

Provided is a method for manufacturing WLCSP devices that includes preparing at least two wafers, each wafer having a plurality of corresponding semiconductor chips, each semiconductor chip having through electrodes formed in the peripheral surface region, forming or applying a solid adhesive region to a central surface region, stacking a plurality of wafers and attaching corresponding chips provided on adjacent wafers with the solid adhesive region and connecting corresponding through electrodes of adjacent semiconductor chips, dividing the stacked wafers into individual chip stack packages, and injecting a liquid adhesive into a space remaining between adjacent semiconductor chips incorporated in the resulting chip stack package. By reducing the likelihood of void regions between adjacent semiconductor chips, it is expected that a method according to the exemplary embodiments of the present invention exhibit improved mechanical stability and reliability.

Method for manufacturing wafer level chip stack package

A method for treating a polyimide surface which includes the steps of amine-treating the polyimide surface and drying the thusly amine-treated polyimide surface. The amine-treating step is preferably carried out by immersing the polyimide in an amine solution which includes an amine and a solvent. The amine is preferably an aliphatic, aromatic, or siloxane amine. The drying step is preferably carried out a temperature of about 50.degree.-200.degree. C. The polyimide is preferably a polyimide having at least one imide functional group in its main chain, and is most preferably a polycondensate of at least one dianhydride and at least one diamine.

Method for treating a polyimide surface

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Seongnam-si, South Korea

Sung-min Sim