Taiwan Semiconductor Manufacturing Comp. Ltd.

Sung-Li Wang

Chia-Hung Chu

Shuen-Shin Liang

Yasutoshi Okuno

Keng-Chu Lin

Hsu-Kai Chang

Ding-Kang Shih

Pang-Yen Tsai

Sey-Ping Sun

Mrunal Abhijith Khaderbad

Clement Hsingjen Wann

Jyh-Cherng Sheu

Hung-Yi Huang

Chih-Wei Chang

Cheng-Wei Chang

Yi-Ying Liu

Chi On Chui

Chin-Hsiang Lin

Chih-Hsin Ko

Pinyen Lin

Neng-Kuo Chen

Yee-Chia Yeo

Ken-Yu Chang

Po-Chin Chang

Meng-Chun Chang

Peng-Wei Chu

Huang-Yi Huang

Fang-Wei Lee

Chun-I Tsai

Gin-Chen Huang

Yi-An Lin

Chen-Feng Hsu

Hau-Yu Lin

Yuting Cheng

Hung-Li Chiang

Lin-Yu Huang

I-Sheng Chen

Chun-Hsien Huang

Yu-Yun Peng

Chien-Shun Liao

Tsungyu Hung

Jhih-Rong Huang

Tzu-Pei Chen

Teng-Chun Tsai

Shen-Nan Lee

Sheng-Tsung Wang

Tzer-Min Shen

Shih-Chuan Chiu

Chien Chang

Yen-Tien Tung

Kuan-Kan Hu

Harry Chien

Tzu Pei Chen

Chuan-Hui Shen

Sai-Hooi Yeong

Cheng-Chi Chuang

Chih-Sheng Chang

Sheng-Chen Wang

Kai-Hsuan Lee

Cheng-Tung Lin

Wei-Yip Loh

Cheng-Yu Yang

Min-Hsiu Hung

Hong-Mao Lee

Jung-Hao Chang

Kan-Ju Lin

Kao-Feng Lin

Chi-Hung Chuang

Pei-Wen Wu

Shu-Lan Chang

Kai-Yi Chu

Yida Li

Chih-Hao Wang

Chia-Hao Chang

Shahaji B More

Ming-Hsi Yeh

Liang-Yin Chen

Shin-Yi Yang

Chia-Cheng Chen

Chih-Chien Chi

Chi-On Chui

Chin-Szu Lee

Chun-Neng Lin

Chun-Hung Wu

Yi-Fang Pai

Bo-Yu Lai

Szu-Hua Wu

Yusuke Oniki

Yan-Ming Tsai

Chun-Hung Liao

Yu Shih Wang

Cheng-Long Chen

Po-Nan Yeh

U-Ting Chiu

Tsun-Jen Chan

Cheng-Wei Lian

Chih-Shiun Chou

Hung Pin Lu

A method for manufacturing a semiconductor device includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench that penetrates through the second dielectric layer, and terminates at the conductive feature; forming a contact layer in the trench and on the conductive feature; etching back the contact layer to form a first via contact feature in the trench, the first via contact feature being electrically connected to the conductive feature; and forming a second via contact feature on the first via contact feature in the trench.

Semiconductor device including stacked via contact and method for manufacturing the same

Low-resistance contacts improve performance of integrated circuit devices that feature epitaxial source/drain regions. The low resistance contacts can be used with transistors of various types, including planar field effect transistors (FETs), FinFETs, and gate-all-around (GAA) FETs. Low-resistance junctions are formed by removing an upper portion of the source/drain region and replacing it with an epitaxially-grown boron-doped silicon germanium (SiGe) material. Material resistivity can be tuned by varying the temperature during the epitaxy process. Electrical contact is then made at the low-resistance junctions.

Epitaxial structure for source/drain contact for semiconductor structure having fin structure

A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Semiconductor device having multi-layer epitaxial structures with different lattice constants

A semiconductor device includes a semiconductor structure, a conductive nitride feature, a third dielectric feature, and a conductive line feature. The semiconductor structure includes a substrate, two source/drain regions disposed in the substrate, a first dielectric feature disposed over the substrate, a gate structure disposed in the first dielectric feature and between the source/drain regions, a second dielectric feature disposed over the first dielectric feature, and a contact feature disposed in the second dielectric feature and being connected to at least one of the source/drain regions and the gate structure. The conductive nitride feature includes metal nitride or alloy nitride, is disposed in the second dielectric feature, and is connected to the contact feature. The third dielectric feature is disposed over the second dielectric feature. The conductive feature is disposed in the third dielectric feature and is connected to the conductive nitride feature opposite to the contact feature.

Semiconductor device including conductive nitride feature and method of making the semiconductor device

Provided are devices with conductive contacts and methods for forming such devices. A method includes forming a lower conductive contact in a dielectric material and over a structure, wherein the lower conductive contact has opposite sidewalls that extend to and terminate at a top surface. The method also includes separating an upper portion of each sidewall from the dielectric material and locating a barrier material between the upper portion of each sidewall and the dielectric material. Further, the method includes forming an upper conductive contact over the lower conductive contact.

Conductive structure interconnects with downward projections

A semiconductor device and a method of forming the same are provided. A method includes forming a gate over a semiconductor structure. An epitaxial source/drain region is formed adjacent the gate. A dielectric layer is formed over the epitaxial source/drain region. An opening extending through the dielectric layer and exposing the epitaxial source/drain region is formed. A conductive material is non-conformally deposited in the opening. The conductive material fills the opening in a bottom-up manner.

Contact plugs for semiconductor device and method of forming same

A semiconductor device includes a source/drain portion, a metal silicide layer disposed over the source/drain portion, and a transition layer disposed between the source/drain portion and the metal silicide layer. The transition layer includes implantation elements, and an atomic concentration of the implantation elements in the transition layer is higher than that in each of the source/drain portion and the metal silicide layer so as to reduce a contact resistance between the source/drain portion and the metal silicide layer. Methods for manufacturing the semiconductor device are also disclosed.

Semiconductor device and method for manufacturing the same

A semiconductor device includes a semiconductor substrate, an epitaxial structure, a silicide structure, a conductive structure, and a protection segment. The epitaxial structure is disposed in the semiconductor substrate. The silicide structure is disposed in the epitaxial structure. The conductive structure is disposed over the silicide structure and is electrically connected to the silicide structure. The protection segment is made of metal nitride, is disposed over the silicide structure, and is disposed between the silicide structure and the conductive structure.

Semiconductor device with conductive liners over silicide structures and method of making the semiconductor device

The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

Liner-free conductive structures with anchor points

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure and over the gate structure, a layer of organometallic material formed through the layer of dielectric material, and a trench conductor layer formed through the layer of dielectric material and in contact with the S/D contact structure and the gate structure. The layer of organometallic material can be between the layer of dielectric material and the trench conductor layer.

Contact structure for semiconductor device

In a method of manufacturing a semiconductor device, a first layer containing an amorphous first material is formed by a deposition process over a semiconductor layer. A second layer containing a metal second material is formed over the first layer. A thermal process is performed to form an alloy layer of the amorphous first material and the metal second material.

Semiconductor device having a uniform and thin silicide layer on an epitaxial source/drain structure

In an embodiment, a device includes: a first insulating fin; a second insulating fin; a nanostructure between the first insulating fin and the second insulating fin; and a gate structure wrapping around the nanostructure, a top surface of the gate structure disposed above a top surface of the first insulating fin, the top surface of the gate structure disposed below a top surface of the second insulating fin.

Transistor gate contacts and methods of forming the same

In some embodiments, the present disclosure relates to an integrated circuit device. A transistor structure includes a gate electrode separated from a substrate by a gate dielectric and a pair of source/drain regions disposed within the substrate on opposite sides of the gate electrode. A lower conductive plug is disposed through a lower inter-layer dielectric (ILD) layer and contacting a first source/drain region. A capping layer is disposed directly on the lower conductive plug. An upper inter-layer dielectric (ILD) layer is disposed over the capping layer and the lower ILD layer. An upper conductive plug is disposed through the upper ILD layer and directly on the capping layer.

Middle-of-line interconnect structure and manufacturing method

A method for manufacturing a semiconductor device includes: forming a lower metal contact in a trench of a first dielectric structure, the lower metal contact having a height less than a depth of the trench and being made of a first metal material; forming an upper metal contact to fill the trench and to be in contact with the lower metal contact, the upper metal contact being formed of a second metal material different from the first metal material and having a bottom surface with a dimension the same as a dimension of a top surface of the lower metal contact; forming a second dielectric structure on the first dielectric structure; and forming a via contact penetrating through the second dielectric structure to be electrically connected to the upper metal contact, the via contact being formed of a metal material the same as the second metal material.

Gate to source drain interconnects

A method includes forming a device region over a substrate; forming a first dielectric layer over the device region; forming an opening in the first dielectric layer; conformally depositing a first conductive material along sidewalls and bottom surfaces of the opening; depositing a second conductive material on the first conductive material to fill the opening, wherein the second conductive material is different from the first conductive material; and performing a first thermal process to form an interface region extending from a first region of the first conductive material to a second region of the second conductive material, wherein the interface region includes a homogeneous mixture of the first conductive material and the second conductive material.

Conductive feature of semiconductor device and method of forming same

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Zhubei, Taiwan

Sung-Li Wang