International Business Machines Corporation

Globalfoundries Inc.

Ultratech, Inc.

Sung Kwon Kang

Sampath Purushothaman

Da-Yuan Shih

Paul Alfred Lauro

Gareth Geoffrey Hougham

George Frederick Walker

Stephen L Buchwalter

Donald W Henderson

Timothy C Reiley

Michael J Palmer

Eugene John O'Sullivan

Robert D Topa

Jeffrey Donald Gelorme

Shaji Farooq

Kamalesh K Srivastava

Anson Jay Call

Kathleen Ann Stalter

Leena Paivikki Buchwalter

Daniel C Edelstein

Keith E Fogel

Voya Rista Markovich

Evan G Colgan

Paul Andrew Moskowitz

Xiao Hu Liu

Frank Robert Libsch

Michael John Brady

Claudius Feger

Gerard McVicker

Madhav Datta

Xiaoxiong Gu

Maurice McGlashan-Powell

Henry Atkinson Nye, Iii

John J Ritsko

Donna S Zupanski-Nielsen

John Ulrich Knickerbocker

Christian Lavoie

Bing Dang

Peter Alfred Gruber

Sri Muthuthamby Sri-Jayantha

Lawrence Shungwei Mok

Jon Alfred Casey

Minhua Lu

Robert L Wisnieff

Jerome J Cuomo

Steven Alan Cordes

Terrence Robert O'Toole

Hien Phu Dang

Arun Sharma

Panayotis Constantinou Andricacos

David Noel Light

Brian Richard Sundlof

Douglas Oliver Powell

S Jay Chey

Roy Arthur Carruthers

Chandrika Prasad

Yu Luo

Anthony P Ingraham

Ajay Prabhakar Giri

Jonathan H Griffith

Wilma Jean Horkans

Peter Jerome Sorce

Thomas P Gall

Jaynal Abedin Molla

Perminder S Bindra

Michael J Sullivan

Keith Thomas Kwietniak

Jungihl Kim

Charles C Goldsmith

Matteo Flotta

Mukta G Farooq

Michael A Gaynes

Hariklia Deligianni

Charles Leon Arvin

Roy Rongqing Yu

John Michael Cotte

Konstantinos I Papathomas

Hilton T Toy

Jane M Shaw

Donald Seton Farquhar

David L Edwards

Eric D Perfecto

Kostas I Papathomas

Bruce Kenneth Furman

Thomas Anthony Wassick

James Gardner Ryan

Leathen Shi

Ho-Ming Tong

Krystyna Waleria Semkow

Mark David Poliks

Frank Louis Pompeo

Subhash Laxman Shinde

Steven Paul Ostrander

Bernd Karl Appelt

Glenn Graham Daves

Erick G Walton

Gangadhara Swami Mathad

Raymond Thomas Galasco

Harry R Bickford

Srinivasa S N Reddy

Karl J Puttlitz, Sr

A method for filling vias with metal includes receiving a substrate having vias, forming a metal plating layer over the vias on a first side of the substrate, fill-plating the vias with a first metal beginning with the metal plating layer on the first side of the substrate and advancing to a second side of the substrate to provide filled vias. The metal plating layer may be subsequently patterned to provide selected circuit connections or chemically-mechanically polished to completely remove the metal plating layer. Forming a metal plating layer over the vias may include filling the vias with a sacrificial filler to enable formation of the metal plating layer and subsequently removing the sacrificial filler via an etching operation or the like. In other embodiments, forming the metal plating layer over the vias is accomplished by bonding a metallic layer onto the first side of the substrate.

Substrate via filling

A contact structure and assembly for a microelectronics device includes first and second electrically conductive contacts being helically shaped. A carrier element is attached to and positioned between the first and second contacts. The first and second contacts are in electrical communication with each other, and the first and second contacts are in a mirror image relationship with each other. A pair of insulating substrates each include electrically conductive members. A contact point on each of the first and second contacts is attached and electrically communicating to respective electrically conductive members such that the first and second electrically conductive contacts between the pair of insulating substrates form an electrically conductive package. A metal layer on the carrier element provides electrical conductivity through a first opening defined by the carrier element between the first and second portions of the helix shaped contact.

Axiocentric scrubbing land grid array contacts and methods for fabrication

Embodiments of the invention include a lead-free solder interconnect structure and methods for making a lead-free interconnect structure. The structure includes a semiconductor substrate having a last metal layer, a copper pedestal attached to the last metal layer, a barrier layer attached to the copper pedestal, a barrier protection layer attached to the barrier layer, and a lead-free solder layer contacting at least one side of the copper pedestal.

Electromigration-resistant lead-free solder interconnect structures

A process comprises manufacturing an electromigration-resistant under-bump metallization (UBM) flip chip structure comprising a Cu layer by applying to the Cu layer a metallic reaction barrier layer comprising NiFe. The solder employed in the flip chip structure comprise substantially lead-free tin. A structure comprises a product produced by this process. In another embodiment a process comprises manufacturing an electromigration-resistant UBM Sn-rich Pb-free solder bump flip chip structure wherein the electromigration-resistant UBM structure comprises a four-layer structure, or a three-layer structure, wherein the four layer structure is formed by providing 1) an adhesion layer, 2) a Cu seed layer for plating, 3) a reaction barrier layer, and 4) a wettable layer for joining to the solder, and the three-layer structure is formed by providing 1) an adhesion layer, 2) a reaction barrier layer, and 3) a wettable layer. In a further embodiment, the reaction barrier layer comprises metals selected from Ni, Fe, Pd, Pt, Co, Cu and their alloys, and combinations thereof. A structure comprises a product produced by the immediately foregoing process.

Electromigration-resistant under-bump metallization of nickel-iron alloys for Sn-rich solder bumps in Pb-free flip-clip

A contact structure and assembly and a method for manufacturing the same for a microelectronics device includes first and second electrically conductive contacts being helically shaped. A carrier element is attached to and positioned between the first and second contacts. The first and second contacts are in electrical communication with each other, and the first and second contacts are in a mirror image relationship with each other. A pair of insulating substrates each include electrically conductive members. A contact point on each of the first and second contacts is attached and electrically communicating to respective electrically conductive members such that the first and second electrically conductive contacts between the pair of insulating substrates form an electrically conductive package. A metal layer on the carrier element provides electrical conductivity through a first opening defined by the carrier element between the first and second portions of the helix shaped contact.

In using Ni(P) and Sn-rich solders in Pb free interconnections, the prevention and control of the formation of intermetallic compound inclusions can be achieved through a reaction-preventative or control layer that is positioned on top of an electroless Ni(P) metallization, such as by application of a thin layer of Sn on the Ni(P) or through the application of a thin layer of Cu on the Ni(P).

Prevention and control of intermetallic alloy inclusions that form during reflow of Pb free, Sn rich, solders in contacts in microelectronic packaging in integrated circuit contact structures where electroless Ni(P) metallization is present

In using Ni(P) and Sn-rich solders in Pb free interconnections, the prevention and control of the formation of intermetallic compound inclusions, can be achieved through a reaction preventive or control layer that is positioned on top of an electroless Ni(P) metallization, such as by application of a thin layer of Sn on the Ni(P) or through the application of a thin layer of Cu on the Ni(P).

Prevention and control of intermetallic alloy inclusions

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting metallurgy including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers

A solder joint comprising a solder capture pad on a substrate having a circuit; and a lead containing or a lead free solder selected from the group comprising Sn&#x2014;Ag&#x2014;Cu solder, Sn&#x2014;Cu solder and Sn&#x2014;Ag solder adhered to the solder capture pad; the solder selected from the group comprising between 0.1 and 6.0 per cent by weight Zn. A solder joint, comprising a solder capture pad on a substrate having a circuit; and a Sn&#x2014;Cu lead free solder adhered to the solder capture pad, the solder comprising between 0.1 and 6.0% by weight Zn. Formation of voids at an interface between the solder and the solder capture pad is suppressed. A method for forming solder joints using the solders.

Modification of solder alloy compositions to suppress interfacial void formation in solder joints

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components. With a two-layer ball-limiting composition comprising an adhesion/reaction barrier layer, wherein the adhesion/reaction barrier layer serves both as an adhesion layer and a reaction barrier layer, the adhesion/reaction barrier layer can be comprised of a material selected from the group consisting of Zr and ZrN.

Interconnections for flip-chip using lead-free solders and having reaction barrier layers

Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers

An interconnection structure suitable for flip-chip attachment of microelectronic device chips to packages, comprising a two, three or four layer ball-limiting composition including an adhesion/reaction barrier layer, and having a solder wettable layer reactive with components of a tin-containing lead free solder, so that the solderable layer can be totally consumed during soldering, but a barrier layer remains after being placed in contact with the lead free solder during soldering. One or more lead-free solder balls is selectively situated on the solder wetting layer, the lead-free solder balls comprising tin as a predominant component and one or more alloying components.

A microelectronic device is made of a semiconductor substrate, a heat generating component in a layer thereof, and a body within the remaining semiconductor substrate. The body is made of materials which have a high thermal inertia and/or thermal conductivity. When high thermal conductivity materials are used, the body acts to transfer the heat away from the substrate to a heat sink.

Microelectronic devices and methods

Growing community of inventors

Chappaqua, NY, United States of America

Sung Kwon Kang