Applied Materials, Inc.

Sung-Kwan Kang

Gill Yong Lee

Chang Seok Kang

Tomohiko Kitajima

Sanjay S Natarajan

Sang Ho Yu

Takehito Koshizawa

Priyadarshi Panda

Susmit Singha Roy

Mukund Srinivasan

Fredrick Fishburn

Nitin K Ingle

Seshadri Ganguli

Jeffrey W Anthis

Fred D Fishburn

Sony Varghese

Jianxin Lei

Shih Chung Chen

Lequn Liu

Wenting Hou

Jorge Pablo Fernandez

Rajib Lochan Swain

Ning Li

Srinivas Gandikota

Mihaela A Balseanu

Qian Fu

Anand N Iyer

Nobuyuki Sasaki

In Seok Hwang

Abdul Wahab Mohammed

Zhaoxuan Wang

A semiconductor manufacturing process for forming a three-dimensional (3D) memory structure and a semiconductor device having a 3D memory structure is described. The 3D memory structure comprises layers of memory cells with L shaped conductive layers where the L shaped conductive layers of each layer are coupled to metal lines disposed above the top or upper most layer such that the memory cells in each layer can be coupled to control circuitry.

L-type wordline connection structure for three-dimensional memory

A memory device architecture, and method of fabricating a three dimensional device are provided. The memory device architecture may include a plurality of memory blocks, arranged in an array, wherein a given memory block comprises: a cell region, the cell region comprising a three-dimensional array of memory cells, arranged in a plurality of n memory cell layers; and a staircase region, the staircase region being disposed adjacent to at least a first side of the cell region, the staircase region comprising a signal line assembly that is coupled to the three-dimensional array of memory cells.

Three dimensional memory device and method of fabrication

A method to produce a layered substrate, which includes the steps of depositing a diffusion barrier layer on the substrate; depositing an underlayer comprising a Group 6 metal on the barrier layer; and depositing a ruthenium layer comprising ruthenium on the underlayer, to produce the layered substrate. A layered substrate is also disclosed.

Ru liner above a barrier layer

Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.

Selection gate separation for 3D NAND

Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.

Three-dimensional dynamic random access memory (DRAM) and methods of forming the same

Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers include a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

3-D DRAM structure with vertical bit-line

Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described where a spacer is formed around each of the bit line contact pillars, the spacer in contact with the spacer of an adjacent bit line contact pillar. A doped layer is then epitaxially grown on the memory stack and bit line is formed on the memory stack. The bit line is self-aligned with the active region.

Method to scale dram with self aligned bit line process

Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

3D DRAM structure with high mobility channel

Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.

Method of testing a gap fill for DRAM

Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

3-D DRAM structures and methods of manufacture

Memory devices and methods of manufacturing memory devices are provided. The device and methods described suppress oxidation of metal layers exposed to ambient oxygen. After an opening is formed, a nitridation process occurs to nitridate the surface of the exposed metal layer inside the opening. The nitridated region formed on the surface of metal layer inside the opening works as a barrier layer for oxygen diffusion. In addition, the nitridated region works as an electrode for charge trap memory cells.

3D-NAND memory cell structure

Memory devices and methods of forming memory devices are described. The memory devices comprise two work-function metal layers, where one work-function layer has a lower work-function than the other work-function layer. The low work-function layer may reduce gate-induced drain leakage current losses. Methods of forming memory devices are also described.

Reducing gate induced drain leakage in DRAM wordline

Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.

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San Jose, CA, United States of America

Sung-Kwan Kang