Samsung Electronics Co., Ltd.

Samsung Sdi Co., Inc.

Seoul National University

Sung-Hyun Choi

Sung-Soo Kim

Young-Soo Kim

Kyung-Hun Jang

Bon-Young Koo

Yong-Suk Tak

Ki-Yeon Park

Hyun-Chul Kim

Sang-Ho Jeon

Seung-Hyun Son

Gi-Gwan Park

Sung-Hee Cho

Hyo-Sun Hwang

Dong-Jun Lee

Gi-Young Kim

Sil-Keun Jeong

Eui-Jeong Hwang

Tae-Jong Lee

Hyoung-Bin Park

Jung-min Kim

Hye-Jung Lee

Myoung-Sup Kim

Mun-Ho Nam

Bok-chun Yun

Gyeom Kim

Sung-Geun Jin

Yong-Hwan Lee

Sang-hyuck Ahn

Hyeon-seok Kim

Won-Oh Seo

Sang-Hyuck Ahn

Jung-Min Kim

Bok-Chun Yun

Hyeon-Seok Kim

A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgas sing prevention pattern sequentially stacked.

Semiconductor devices and methods of manufacturing the same

A method of forming a SiOCN material layer, a material layer stack, a semiconductor device, a method of fabricating a semiconductor device, and a deposition apparatus, the method of forming a SiOCN material layer including providing a substrate; providing a silicon precursor onto the substrate; providing an oxygen reactant onto the substrate; providing a first carbon precursor onto the substrate; providing a second carbon precursor onto the substrate; and providing a nitrogen reactant onto the substrate, wherein the first carbon precursor and the second carbon precursor are different materials.

Methods of fabricating a SiOCN layer using a first and second carbon precursor, the first carbon precursor being different from the second carbon precursor

An integrated circuit device includes a fin type active area protruding from a substrate and having an upper surface at a first level; a nanosheet extending in parallel to the upper surface of the fin type active area and comprising a channel area, the nanosheet being located at a second level spaced apart from the upper surface of the fin type active area; a gate disposed on the fin type active area and surrounding at least a part of the nanosheet, the gate extending in a direction crossing the fin type active area; a gate dielectric layer disposed between the nanosheet and the gate; a source and drain region formed on the fin type active area and connected to one end of the nanosheet; a first insulating spacer on the nanosheet, the first insulating spacer covering sidewalls of the gate; and a second insulating spacer disposed between the gate and the source and drain region in a space between the upper surface of the fin type active area and the nanosheet, the second insulating spacer having a multilayer structure.

Integrated circuit device and method of manufacturing the same

A semiconductor device includes an active fin on a substrate, a gate structure on the active fin, a gate spacer structure on a sidewall of the gate structure, and a source/drain layer on at least a portion of the active fin adjacent the gate spacer structure. The gate spacer structure includes a wet etch stop pattern, an oxygen-containing silicon pattern, and an outgassing prevention pattern sequentially stacked.

A semiconductor device includes a substrate including an active fin structure, a plurality of gate structures, a first spacer on sidewalls of each of the gate structures, and a second spacer on sidewalls of the first spacer. The active fin structure may extend in a first direction and including a plurality of active fins with adjacent active fins divided by a recess. Each of the plurality of gate structures may extend in a second direction crossing the first direction, and may cover the active fins. The first spacer may include silicon oxycarbonitride (SiOCN), and may have a first carbon concentration. The second spacer may include SiOCN and may have a second carbon concentration which is different from the first carbon concentration. The semiconductor device may have a low parasitic capacitance and good electrical characteristics.

A plasma display panel (PDP) comprises: a front substrate and a rear substrate which face each other; and a barrier wall which is interposed between the front substrate and the rear substrate, which includes base portions arranged on either side of a main discharge space, and protruding portions protruding on the base portions, respectively, and which defines stepped spaces on either side of the main discharge space. The stepped spaces are formed according to stepped surfaces formed by the base portions and the protruding portions. The PDP further comprises a pair of a scan electrode and a sustain electrode which generate a mutual discharge through the main discharge space. A channel space is defined by outer walls of the protruding portions on either side of the main discharge space, and an external light absorbing layer covers the channel space.

Plasma display panel characterized by high efficiency

A plasma display panel (PDP) and a method of manufacturing the same with improved luminous efficiency. The PDP includes: a first substrate; a second substrate facing the first substrate; a plurality of sustain electrode pairs between the first substrate and the second substrate and extending in a first direction; a plurality of address electrodes on the second substrate and extending in a second direction crossing the first direction; a first dielectric layer on the second substrate for covering the address electrodes; a discharge enhancement layer on the first dielectric layer; a plurality of barrier ribs on the discharge enhancement layer and defining discharge cells between the first and second substrates; and phosphor layers in the discharge cells, wherein the discharge enhancement layer has an opening in each of the discharge cells, and wherein the barrier ribs have a roughness less than that of the discharge enhancement layer.

Plasma display panel and method of manufacturing the same

A plasma display panel is disclosed. The plasma display panel has discharge cells which each have a range of widths between the first substrate and the second substrate. In addition, the discharge spaces are separated by non-discharge spaces having heights which are less than the heights of the discharge spaces.

Plasma display panel

A plasma display panel is disclosed. The plasma display panel has discharge cells which each have a range of widths between the first substrate and the second substrate. In addition, the discharge spaces are separated by non-discharge spaces having heights substantially the same as the heights of the discharge spaces.

Growing community of inventors

Suwon-si, South Korea

Sung-Hyun Choi