Taiwan Semiconductor Manufacturing Comp. Ltd.

Sung-Hui Huang

Shang-Yun Hou

Kuan-Yu Huang

Chen-Hua Douglas Yu

Chi-Hsi Wu

Hsing-Kuo Hsia

Shu-Chia Hsu

Li-Chung Kuo

Ying-Ching Shih

Kuo-Chiang Ting

Jui-Hsieh Lai

Chien-Yuan Huang

Yushun Lin

Hsiang-Fan Lee

Tien-Yu Huang

Heh-Chang Huang

Pai-Yuan Li

Chih-Wei Wu

Tsung-Yu Chen

Pai Yuan Li

Wen-Wei Shen

Der-Chyang Yeh

Hsien-Pin Hu

Chin-Fu Kao

Kuo-Ching Hsu

Wei-Ming Chen

Cheng-Hsien Hsieh

Jui Hsieh Lai

Szu-Po Huang

Wen-Hsin Wei

Chun Hua Chang

Wen-Cheng Chen

Cheng-Chieh Li

Yu-Yun Huang

Chih-Chieh Hung

Da-Cyuan Yu

Wan-Yu Lee

Sao-Ling Chiu

Hung-Pin Chang

Yu-Jen Cheng

Long Hua Lee

Yu-Wei Chen

Tzu-Kai Lan

Wen-Yao Chang

Pin-Tso Lin

Yi-Wei Liu

Ying-Shin Han

Hsiang-fan Lee

Leu-Jen Chen

Shou-Chih Yin

Yu-Shun Lin

Shu Chia Hsu

Ming-Fa Chen

Dian-Hau Chen

Sen-Bor Jan

Yuan-Hung Liu

Kung-Chen Yeh

Wen Ting Tsai

Bin-Yuan Hung

Ching Wei Hsieh

A method of forming a semiconductor package includes: forming a first package component including a first and a second conductive bumps; forming a second package component including a third and a fourth conductive bumps, where dimensions of the first and second conductive bumps are less than dimensions of the third and fourth conductive bumps; and forming a first and a second joint structures to bond the second package component to the first package component. A first angle between an exposed sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the sidewall of the first conductive bump is less than a second angle between an exposed sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the sidewall of the second conductive bump.

Joint structure in semiconductor package and manufacturing method thereof

A package structure is provided. The package structure includes a semiconductor die structure over a substrate and bonding structures between the semiconductor die and the substrate. The package structure also includes multiple solder elements over the substrate. The solder elements together surround the semiconductor die structure, and each of the solder elements is longer than a side of the semiconductor die structure. The package structure further includes an underfill material surrounding the bonding structures. The underfill material is substantially confined within a region surrounded by the solder elements. The underfill material is in direct contact with at least one of the solder elements.

Package structure with underfill

An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.

Integrated circuit package and method of forming same

A structure including a photonic integrated circuit die, an electric integrated circuit die, a semiconductor dam, and an insulating encapsulant is provided. The photonic integrated circuit die includes an optical input/output portion and a groove located in proximity of the optical input/output portion, wherein the groove is adapted for lateral insertion of at least one optical fiber. The electric integrated circuit die is disposed over and electrically connected to the photonic integrated circuit die. The semiconductor dam is disposed over the photonic integrated circuit die. The insulating encapsulant is disposed over the photonic integrated circuit die and laterally encapsulates the electric integrated circuit die and the semiconductor dam.

Optical transceiver and manufacturing method thereof

A device includes a first package connected to an interconnect substrate, wherein the interconnect substrate includes conductive routing; and a second package connected to the interconnect substrate, wherein the second package includes a photonic layer on a substrate, the photonic layer including a silicon waveguide coupled to a grating coupler and to a photodetector; a via extending through the substrate; an interconnect structure over the photonic layer, wherein the interconnect structure is connected to the photodetector and to the via; and an electronic die bonded to the interconnect structure, wherein the electronic die is connected to the interconnect structure.

Photonic semiconductor device and method of manufacture

In an embodiment, an interposer has a first side, a first integrated circuit device attached to the first side of the interposer with a first set of conductive connectors, each of the first set of conductive connectors having a first height, a first die package attached to the first side of the interposer with a second set of conductive connectors, the second set of conductive connectors including a first conductive connector and a second conductive connector, the first conductive connector having a second height, the second conductive connector having a third height, the third height being different than the second height, a first dummy conductive connector being between the first side of the interposer and the first die package, an underfill disposed beneath the first integrated circuit device and the first die package, and an encapsulant disposed around the first integrated circuit device and the first die package.

Semiconductor die package and method of manufacture

A semiconductor device including a first semiconductor die, a second semiconductor die, an insulating encapsulation and a warpage control pattern is provided. The first semiconductor die includes an active surface and a rear surface opposite to the active surface. The second semiconductor die is disposed on the active surface of the first semiconductor die. The insulating encapsulation is disposed on the active surface of the first semiconductor die and laterally encapsulates the second semiconductor die. The warpage control pattern is disposed on and partially covers the rear surface of the first semiconductor die.

Package structure and fabricating method thereof

A semiconductor device includes a substrate, an electronic component, a stiffener ring and an adhesive ring. The substrate has a first surface and a second surface opposite to the first surface. The electronic component is over the first surface of the substrate. The stiffener ring is over the first surface of the substrate. The stiffener ring includes a plurality of side parts and a plurality of corner parts coupled to the side parts. Heights of the corner parts are less than heights of the side parts. The adhesive ring is interposed between the first surface of the substrate and the stiffener ring. The adhesive ring includes a plurality of side portions and a plurality of corner portions coupled to the side portions. Thicknesses of the side portions are less than thicknesses of the corner portions.

Semiconductor device

Semiconductor package includes interposer, dies, encapsulant. Each die includes active surface, backside surface, side surfaces. Backside surface is opposite to active surface. Side surfaces join active surface to backside surface. Encapsulant includes first material and laterally wraps dies. Dies are electrically connected to interposer and disposed side by side on interposer with respective backside surfaces facing away from interposer. At least one die includes an outer corner. A rounded corner structure is formed at the outer corner. The rounded corner structure includes second material different from first material. The outer corner is formed by backside surface and a pair of adjacent side surfaces of the at least one die. The side surfaces of the pair have a common first edge. Each side surface of the pair does not face other dies and has a second edge in common with backside surface of the at least one die.

Semiconductor package and manufacturing method thereof

A package assembly includes a package substrate including a first die that includes a photonic integrated circuit, a second die located on the first die, the second die including an electronic integrated circuit electrically connected to the photonic integrated circuit, and an interposer module on the package substrate, at least a portion of the interposer module being located on the first die and electrically connected to the photonic integrated circuit.

Photonic silicon spatial beam transformer integrated on 3DIC package and methods for forming the same

A semiconductor package includes first and second package components stacked upon and electrically connected to each other, and first and second joint structures. The first package component includes first and second conductive bumps, the second package component includes third and fourth conductive bumps having dimensions greater than those of the first and second conductive bumps. The first joint structure partially covers the first and third conductive bumps. The second joint structure partially covers the second and the fourth conductive bumps. A first angle between a sidewall of the first conductive bump and a tangent line at an end point of a boundary of the first joint structure on the first conductive bump is greater than a second angle between a sidewall of the second conductive bump and a tangent line at an end point of a boundary of the second joint structure on the second conductive bump.

A method includes bonding a first package component over a second package component, dispensing a first underfill between the first package component and the second package component, and bonding a third package component over the second package component. A second underfill is between the third package component and the second package component. The first underfill and the second underfill are different types of underfills.

Packages with multiple types of underfill and method forming the same

A package structure includes a circuit substrate and a semiconductor device. The semiconductor device is disposed on and electrically connected to the circuit substrate. The semiconductor device includes an interconnection structure, a semiconductor die, an insulating encapsulant, a protection layer and electrical connectors. The interconnection structure has a first surface and a second surface. The semiconductor die is disposed on the first surface and electrically connected to the interconnection structure. The insulating encapsulant is encapsulating the semiconductor die and partially covering sidewalls of the interconnection structure. The protection layer is disposed on the second surface of the interconnection structure and partially covering the sidewalls of the interconnection structure, wherein the protection layer is in contact with the insulating encapsulant. The electrical connectors are disposed on the protection layer, wherein the interconnection structure is electrically connected to the circuit substrate through the plurality of electrical connectors.

Package structure and method of fabricating the same

A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.

Semiconductor package and method of forming the same

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a bump and a first dummy bump between the chip and the substrate. The bump is electrically connected between the chip and the substrate, the first dummy bump is electrically insulated from the substrate, and the first dummy bump is wider than the bump. The chip package structure includes a first dummy solder layer under the first dummy bump and having a curved bottom surface facing and spaced apart from the substrate.

Chip package structure

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Dongshan, Taiwan

Sung-Hui Huang