Advanced Semiconductor Engineering, Inc.

Sung-Fei Wang

Chaur-Chin Yang

Su Tao

Yu-Fang Tsai

Jian-Wen Chen

Tsung-Ming Pai

Kuang-Hui Chen

Meng-Hui Lin

Ming-Lun Ho

A flip-chip package comprises a substrate with an opening. A dummy die is disposed onto the substrate corresponding to the opening so as to form a composite chip carrier with a chip cavity. The dummy die has a redistribution layer which includes a plurality of flip-chip pads for flip-chip connection of a chip and a plurality of connecting pads around the dummy die for connecting the substrate. The dummy die mounts at least a chip by flip chip connection for being an electrical interface medium between the chip and the substrate in order to achieve thinner package thickness, high heat dissipation, fine pitch flip-chip mounting and eliminating flip-chip stress on the chip.

Flip-chip package

A flip chip stacked package mainly comprises a carrier, a lower chip, an upper chip, a plurality of bumps, a plurality of bonding wires and a supporter. The supporter is attached to the lower surface of the carrier via an adhesive and covers the opening of the carrier. Thus, the lower chip can be disposed in the opening. In addition, the lower chip is electrically flip-chip bonded to the upper chip via the bumps and electrically connected to the carrier via the bonding wires. Accordingly, the heat generated from the lower chip can be transmitted to outside via the supporter. Furthermore, the upper chip is directly exposed to outside so that the capability of the heat dissipation will be enhanced.

Flip chip stacked package

A multi-chips stacked package at least comprises a substrate, a lower chip, an upper chip, an adhesive layer, a supporting body and an encapsulation. The lower chip is disposed on the substrate and the upper chip is attached to the lower chip via the adhesive layer. In addition, the lower chip and the upper chip are electrically connected to the substrate via first electrically conductive wires and second electrically conductive wires respectively. Furthermore, the supporting body is disposed on the lower chip and at the periphery of the upper surface of the lower chip, and covered by the upper chip. The top of the supporting body is apart from the back surface of the upper chip with a distance. Accordingly, when the second electrically conductive wires are bonded the upper chip to the substrate with a larger bonding force to cause the upper chip to be tilted more, the supporting body will support the upper chip and prevent the upper chip from contacting the first electrically conductive wires.

Multi-chips stacked package

A multi-chips stacked package mainly comprises a substrate, a first lower chip, a second lower chip, an upper chip and a carrier. The substrate has an upper surface, and the first lower chip and the second lower chip are disposed on the upper surface of the substrate and electrically connected to the substrate. The carrier is disposed on and electrically connected to the first lower chip and the second lower chip simultaneously, and the upper chip is mounted on the carrier. Moreover, the upper chip is electrically connected to the substrate through the carrier, the first lower chip or the second lower chip.

A method for bonding a heat sink to a chip package structure is disclosed. The chip package structure at least comprises a chip and a stiffener ring around the chip. Both the chip and the stiffener ring are set up on a substrate. The heat sink comprises a first protruding section located at a position corresponding to the chip and a plurality of second protruding sections located at positions corresponding to the stiffener ring. The method includes forming a gluing layer on the first protruding section and the second protruding sections of the heat sink and pressing the heat sink against the chip package structure to bond the heat sink and the chip package together. The first protruding section of the heat sink is attached to the chip and the second protruding sections are attached to the stiffener ring.

Heat sink for chip package and bonding method thereof

A semiconductor package with a heat spreader is described, including a first chip, a second chip, a heat spreader and a substrate. The first chip has an active surface over which the second chip is attached. The heat spreader is attached over the first chip. The first chip is bonded onto the substrate.

Semiconductor package with a heat spreader

The present invention relates to a stacked semiconductor chip package comprising a substrate, a first chip, a plate, and a second chip The first chip is mounted on the substrate. The second chip comprises two opposed longitudinal sides defining a first length. The plate is mounted between the first chip and the second chip, and connects the first chip and the second chip. Corresponding to the two longitudinal sides of the second chip, the plate has two opposed longitudinal sides defining a second length. The second length is larger than the first length to expose the opposed longitudinal sides of the plate. An overflow adhesive portion is formed between the plate and the second chip, and the overflow adhesive portion exposes on the plate. Therefore, the testing instrument can detect the size of the overflow adhesive portion and the thickness of the adhesive layer so as to control the quality of the stacked semiconductor chip package. The adhesion strength between the stacked chip and the plate can be augmented to raise the reliability of the stacked semiconductor chip package product.

Stacked semiconductor chip package

A flip chip package includes a substrate, a flip chip, a thermal interface material and a heat sink. The flip chip is mounted on the substrate. The thermal interface material is applied on the back surface of the flip chip. The back surface of the flip chip includes a region uncovered by the thermal interface material. The opening exposes the uncover region of the back surface of the flip chip for measuring the height of the back surface. Also the opening has an inner sidewall above the back surface for fillet bonding of the thermal interface material. Therefore the bond line thickness (BLT) of the thermal interface material can be measured and calculated.

Flip chip package capable of measuring bond line thickness of thermal interface material

A multi-chips stacked package mainly comprises a substrate, a lower chip, an upper chip, an intermediate chip, a plurality of bumps and an encapsulation. Therein, the lower chip is disposed on the substrate; the bumps connect the lower chip and the intermediate chip; the upper chip and the lower chip are electrically connected to the substrate via a plurality of first electrically conductive wires and second electrically conductive wires respectively. The bumps can support the intermediate chip more firmly, so the top of the intermediate chip can be kept in counterpoise and higher than the peak of the first wires. Accordingly, the intermediate chip will be prevented from being tilted excessively to cause the upper chip to be contacted to the first electrically conductive wires. Thus, the first electrically conductive wires can be prevented from being damaged when the upper chip is wire bonded to the substrate.

A high density semiconductor package comprises a substrate, a first package module and a plurality of second package modules. The substrate has a surface on which the first package module and the second package modules are disposed, wherein the second package modules surround the first package module.

High density semiconductor package

A thermal enhance multi-chips module package mainly comprises an assembly substrate, a first assembly package, a second assembly package, a heat dissipation board, and a thermally conductive metal ring. The first assembly package and the second assembly package are disposed on the upper surface and the lower surface of the assembly substrate respectively; and the thermally conductive metal ring is disposed at the periphery of the upper surface of the heat dissipation board and encompasses the second assembly package. The second assembly package has a logic chip therein and generates a lot of heat, and the heat dissipation board can transmit the heat to the outside through the thermally conductive metal ring so as to prevent the excessive heat from transmitting to the motherboard and accumulating in the motherboard. Accordingly, the motherboard can be avoided damaging.

Thermal enhance MCM package

A multi-chips package at least comprises a substrate, an upper chip, a lower chip, a reinforced device, and a plurality of electrically conductive bumps. The upper chip is flip-chip bonded to the upper surface of the substrate and the lower chip is accommodated in the opening and flip-chip bonded to the upper chip. Furthermore, the reinforced device is mounted onto the back surface of the lower chip and the lower surface of the substrate. The coefficient of the thermal expansion of the reinforced device ranges from the coefficient of the thermal expansion of the substrate to the coefficient of the thermal expansion of the chip. In such a manner, the reinforced device can constrain the thermal deformation of the substrate so as to prevent the electrically conductive bumps connecting the first chip and the substrate from being damaged.

Multi-chips package

A multi-chip stack flip-chip package comprises a substrate and a chip assembly on the substrate. The chip assembly includes a dummy chip and a flip chip. The dummy chip has a redistribution layer that has a plurality of bump pads for mounting the flip chip, a plurality of peripheral pads for electrically connecting to the substrate, and a plurality of integrated circuit traces connecting the bump pads with the peripheral pads. The dummy chip is disposed between the flip chip and the substrate as an electrically connecting interface between the flip chip and the substrate for multi-chip flip-chip stack and fine pitch flip-chip mounting.

Multi-chip stack flip-chip package

A stacked chip scale package. The stacked chip scale package has a substrate having mounting pads arranged to lie close to the rectangular sides. A smaller silicon chip is stacked on the active surface of a larger silicon chip and the larger silicon chip rest on the substrate. The mounting pads on the substrate are distributed around the periphery of the lower silicon chip. Both the upper silicon chip and the lower silicon chip have only one pair of opposite sides having bonding pads. The pair of edges of the upper silicon chip with bonding pads nearby is parallel to the pair of edges of the lower silicon chip without bonding pads. The bonding pads on the upper chip and the lower chip are electrically connected to their neighboring mounting pads through conductive wires. The conductive wires, the upper silicon chip, the lower silicon chip and a portion of the substrate are enclosed by packaging material.

Stacked chip scale package

A stacked dies include a substrate, a lower chip and an upper chip. A plurality of upper wires have the bent portion at the bonding pad of the substrate to reduce the height and increase the strength of the wire so as to increase the reliability of the product and to increase the space between the lower wire and the upper wire for reduction cross talk. A method of making low profile upper wire connection comprising steps of: after an upper wire is connected to a first bonding point, a capillary is moved straight up a first distance, and then the capilairy is moved away from a second bonding point thus making a first reverse action to bend the wire in an appropriate angle so as to form the first bent point. The capillary is again raised a second distance and moved downward a second reverse action to bend the upper wire by an appropriate angle so as to form the second bent point. The capillary is raised a third distance and then the capillary is moved away the second bonding point thus making an action to bend the wire in an appropriate angle so as to form the third bent point. The capillary is further raised a fourth distance. The capillary is raised to the second bonding point to extend the length of two wire ends which is enough to make a wire loop, amd then the capillary is moved down to the second bonding point where the bonding is performed.

Growing community of inventors

Kaohsiung, Taiwan

Sung-Fei Wang