Samsung Electronics Co., Ltd.

Infineon Technologies Ag

Sung Dong Cho

Sang Jun Park

Eun Ji Kim

Dae Suk Lee

Hak Seung Lee

Dong Chan Lim

Kwang Wuk Park

Bum Ki Moon

Woo Jin Jang

Hyung Woo Kim

A semiconductor device includes a substrate, an interlayer insulating layer on the substrate, a first etch stop layer on the substrate, a first through-silicon-via (TSV) configured to pass vertically through the substrate and the interlayer insulating layer, and a second TSV configured to pass vertically through the substrate, the interlayer insulating layer, and the first etch stop layer, wherein the second TSV has a width greater than that of the first TSV.

Semiconductor device including TSV and method of manufacturing the same

Methods of forming electrical interconnects include forming a copper pattern on a semiconductor substrate and then forming an electrically insulating capping layer on the copper pattern and an interlayer insulating layer on the electrically insulating capping layer. A contact hole is then formed, which extends through the interlayer insulating layer and the electrically insulating capping layer and exposes an upper surface of the copper pattern. An electroless plating step is then performed to form a copper pattern extension onto the exposed upper surface of the copper pattern. The copper pattern extension may have a thickness that is less than a thickness of the electrically insulating capping layer, which may be formed as a SiCN layer.

Methods of forming electrical interconnects using electroless plating techniques that inhibit void formation

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Sung Dong Cho