Intel Corporation

Intel Corportion

Sundar V Pathy

James Edward Neeb

Shelby G Rollins

Christopher J Nelson

Yu Amos Zhang

Timothy J Callahan

Stephen Sturges

Bradly L Inman

Nathan S Blackwell

Matthew Hendricks

Jesse Armagost

Matthew Boelter

Hiren V Tilala

Jared Pager

Geoffrey Kelly

Embodiments described herein may be directed to receiving a plurality of data captured, respectively, by a plurality of test instruments coupled to a device under test, wherein a plurality of data elements within, respectively, the plurality of captured data are associated with a timestamp based upon a time a data element was captured. Embodiments may also analyze the received plurality of data captured, respectively, by the one or more test instruments, and graphically display at least a portion of the analyzed plurality of captured data to a user. Other embodiments may be identified herein.

Debug tool for test instruments coupled to a device under test

Embodiments herein relate to apparatus, systems, and methods to compress a test pattern onto a field programmable gate array to test a device under test. This may include identifying values of a plurality of drive pins for a plurality of test cycles to apply to an input of the DUT for each of the plurality of test cycles, identifying values of a plurality of compare pins for the plurality of test cycles to compare an output of the DUT, respectively, for each of the plurality of test cycles, analyzing the identified values, compressing, based on the analysis, the values of the plurality of drive pins and the plurality of compare pins, and storing the compressed values on the FPGA.

Compressed test patterns for a field programmable gate array

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Chandler, AZ, United States of America

Sundar V Pathy