Samsung Electronics Co., Ltd.

Kt Corporation

Intellectual Discovery Co., Ltd.

Samung Electronics Co., Ltd

Sun-Jung Lee

Hong-Jae Shin

Tae-Hyo Ahn

Sang-Youn Lee

Tae-Kyun Kim

Young-Sung Kim

Yeon-Dae Kim

Hae-Young Song

Won-Taik Hwang

Yoon-Kyoo Jung

Sung-Uk Jang

Da-Il Eom

Jung-Hun Choi

Jeong-Nam Han

Hyeon-Deok Lee

Seung-Pil Chung

Ki-Chul Park

Kun-tack Lee

Soo-geun Lee

Chan-Jin Park

Im-Soo Park

Seung-man Choi

Sung-woo Kang

Young-Mook Oh

Kyu-hwan Chang

Bong-Seok Suh

Mu-kyeng Jung

Andrew-Tae Kim

Moon-hee Lee

Chung-Hwan Shin

Kwang-wook Lee

Bong-seok Suh

Kyu-whan Chang

An integrated circuit device includes a source/drain region having a recess in its top, a contact plug extending on the source/drain region from within the recess, and a metal silicide layer lining the recess and having a first portion covering a bottom of the contact plug and a second portion that is integral with the first portion and covers a lower part of sides of the contact plug. The second portion of the silicide layer may have a thickness different from a thickness of the first portion of the silicide layer. The silicide layer is formed at a relatively low temperature to offer an improved resistance characteristic as between the source/drain region and the contact plug.

Integrated circuit device and method of manufacturing the same

A digital processing device capable of receiving an additional service is disclosed. In one aspect, a digital processing device includes i) an input unit, inputting a signal, ii) a subscriber identity unit, storing an identity code of a communication operator and generating a communication network access request message, iii) an additional service identity unit, storing an identity code of an additional service operator and generating an additional service request message and v) a control unit, generating a control signal allowing one of the subscriber identity unit and the additional service identity unit to be selectively driven. In accordance with at least one inventive embodiment, a user of the digital processing device can receive an additional service without his or her subscription to a specific communication operator and use various additional services in addition to the additional services provided by the subscribed communication operator.

Digital device and method for providing additional service by using the same

A semiconductor device includes an active fin formed to extend in a first direction, a gate formed on the active fin and extending in a second direction crossing the first direction, a source/drain formed on upper portions of the active fin and disposed at one side of the gate, an interlayer insulation layer covering the gate and the source/drain, a source/drain contact passing through the interlayer insulation layer to be connected to the source/drain and including a first contact region and a second contact region positioned between the source/drain and the first contact region, and a spacer layer formed between the first contact region and the interlayer insulation layer. A width of the second contact region in the first direction is greater than the sum of a width of the first contact region in the first direction and a width of the spacer layer in the first direction.

Fin-FET semiconductor device with a source/drain contact having varying different widths

A test apparatus includes a plurality of pairs of test contacts on a semiconductor substrate; a first test structure which includes a plurality of first test interconnection layers and a first body interconnection layer that is electrically connected to the first test interconnection layers, each of the first test interconnection layers being electrically connected to at least one test contact; and a second test structure which includes a plurality of second test interconnection layers and a second body interconnection layer that is electrically connected to the second test interconnection layers, each of the second test interconnection layers being electrically connected to at least one test contact.

Test apparatus for determining if adjacent contacts are short-circuited and semiconductor integrated circuit devices that include such test apparatus

A test device, SRAM test device, semiconductor integrated circuit, and methods of fabricating the same are provided. The test device may include a first test active region extending in one direction on a semiconductor substrate, a second test active, apart from the first test active region, extending in one direction on a semiconductor substrate, a plurality of test gate lines crossing the test active regions, a plurality of test contacts on at least one of the test active regions and test gate lines, a plurality of conducting regions electrically connecting the test contacts, and a plurality of conductive wiring lines interconnecting the plurality of test contacts, wherein an open contact chain, which electrically connects the plurality of test contacts, is formed.

Test device, SRAM test device, semiconductor integrated circuit device and methods of fabricating the same

A method of forming a wiring layer of a semiconductor device, includes forming a first interlayer insulating layer to have a first thickness corresponding to a part of the thickness of an interlayer insulating layer that is to be formed on a support layer and forming a first contact plug in the first interlayer insulating layer. The method further includes forming a second interlayer insulating layer to have a second thickness on the first contact plug and the first interlayer insulating layer, thereby forming the interlayer insulating layer, wherein the second thickness corresponds to the rest of the thickness of the interlayer insulating layer, and forming a second contact plug connected to the first contact plug in the second interlayer insulating layer, thereby forming a local wiring layer including the first contact plug and the second contact plug.

Method of forming wiring layer of semiconductor device

A semiconductor device that prevents gate spacer stress and physical and chemical damages on a silicide region, and a method of manufacturing the same, according to an exemplary embodiment of the present invention, includes a substrate, isolation regions formed in the substrate, a gate pattern formed between the isolation regions on the substrate, an L-type spacer adjacent to the sidewall of the gate pattern and extended to the surface of the substrate, source/drain silicide regions formed on the substrate between the end of the L-type spacer extended to the surface of the substrate and the isolation regions, via plugs electrically connected with the source/drain silicide regions, an interlayer dielectric layer which is adjacent to the L-type spacer and which fills the space between the via plugs layer formed on the gate pattern and the substrate, and a signal-transfer line formed on the interlayer dielectric layer.

Semiconductor device free of gate spacer stress and method of manufacturing the same

A method for removing an oxide layer such as a natural oxide layer and a semiconductor manufacturing apparatus which uses the method to remove the oxide layer. A vertically movable susceptor is installed at the lower portion in a processing chamber and a silicon wafer is loaded onto the susceptor when it is at the lower portion of the processing chamber. The air is exhausted from the processing chamber to form a vacuum condition therein. A hydrogen gas in a plasma state and a fluorine-containing gas are supplied into the processing chamber to induce a chemical reaction with the oxide layer on the silicon wafer, resulting in a reaction layer. Then, the susceptor is moved up to the upper portion of the processing chamber, to anneal the silicon wafer on the susceptor with a heater installed at the upper portion of the processing chamber, thus vaporizing the reaction layer. The vaporized reaction layer is exhausted out of the chamber. The oxide layer can be removed with a high selectivity while avoiding damage or contamination of the underlying layer.

Method of removing oxide layer and semiconductor manufacturing apparatus for removing oxide layer

A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.

Method of forming a metal interconnection of a semiconductor device, and metal interconnection formed by such method

Copper-plating elecrolyte containing polyvinylpyrrolidone and method for forming a copper interconnect

Growing community of inventors

Seoul, South Korea

Sun-Jung Lee