Skhynix Inc.

Semes Co., Ltd.

Sun Joo Park

Heon Yong Chang

Daehyun Kim

Sang Gon Lee

Saewon Na

A semiconductor wafer includes at least one chip region disposed in a substrate, a first chip guard disposed over the substrate in a chip sealing region positioned outside the at least one chip region, a second chip guard disposed over the substrate in a scribe lane region positioned outside the chip sealing region, and a test circuit pattern disposed in the scribe lane region and including a ground line electrically connected to a ground well in the substrate. The second chip guard includes a ground wiring layer electrically connected to the ground line of the test circuit pattern.

Semiconductor wafer including chip guard

An apparatus for treating a substrate includes a process chamber having a treatment space therein, a support unit that supports the substrate in the treatment space, a gas supply unit that supplies a process gas into the treatment space, an RF power supply that supplies an RF signal to excite the process gas into plasma, and a matching circuit connected between the RF power supply and the process chamber. The matching circuit includes an impedance matching device that performs impedance matching and a harmonic removal device that removes harmonics caused by the RF power supply. The matching circuit operates in a first mode when the harmonics caused by the RF power supply are sensed and in a second mode when the harmonics caused by the RF power supply are not sensed.

Apparatus and method for treating substrate

A dummy active region is formed in a region in which a gate contact for supplying operation power to the buried gate is formed, and a PN junction diode connected to the gate contact in a reverse bias direction is formed in the dummy active region. Current leakage, in which current flows out toward a substrate, is prevented even when misalignment of the gate contact occurs.

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Seoul, South Korea

Sun Joo Park