Samsung Electronics Co., Ltd.

Sun-Hye Lee

Tae-Hun Kim

Dae-Young Choi

Jin-Woo Park

Mi-Yeon Kim

Yang-Hoon Ahn

Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.

Stacked packages having through hole vias

A semiconductor package apparatus includes a first semiconductor package including a first semiconductor chip, a first substrate, a first terminal, and a first signal transfer medium, and a second semiconductor package including a second semiconductor chip, a second substrate, a second terminal, and a second signal transfer medium. At least one package connecting solder ball is located between the first terminal and the second terminal. A first solder ball guide member is positioned around the first terminal of the first substrate and includes a first guide surface for guiding a shape of the package connecting solder ball.

Semiconductor package apparatus

Method of forming package-on-package and device related thereto

Growing community of inventors

Cheongju-si, South Korea

Sun-Hye Lee