Globalfoundries Inc.

Applied Materials, Inc.

International Business Machines Corporation

Sukwon Hong

Min Gyu Sung

Jingmei Liang

Chanro Park

Hoon Sik Kim

Su Chen Fan

William James Taylor, Jr

Ruilong Xie

Nitin K Ingle

Kwan-Yong Lim

Abhijit Basu Mallick

Toan Q Tran

Xinyuan Dou

Hiroshi Hamana

Sandeep Gaan

Anjana M Patel

Tao Han

Shimpei Yamaguchi

Carlos Chacon

Satyajit Shinde

At least one method, apparatus and system are disclosed for forming a fin field effect transistor (finFET) while reducing oxidization and fin critical dimension loss. A plurality of fins of a transistor are formed. A hard mask layer is formed on top of the fins. A first liner layer is formed over the fins and the hard mask layer. A partial deposition process is performed for depositing a first insulation material in a first portion of a channel between the fins. A second liner layer is formed above the fins, the first insulation material, and the channel. A second insulation material is deposited above the second liner layer. A fin reveal process is performed for removing the second insulation material to a predetermined height. An etch process is performed for removing the hard mask layer and the first and second liner layers above the predetermined height.

Methods, apparatus and system for local isolation formation for finFET devices

Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200&#xb0; C. with a process gas including Nand HO.

Methods for fabricating integrated circuits using flowable chemical vapor deposition techniques with low-temperature thermal annealing

An interconnect structure includes an insulator stack on an upper surface of a semiconductor substrate. The insulator stack includes a first insulator layer having at least one semiconductor device embedded therein and an etch stop layer interposed between the first insulator layer and a second insulator layer. At least one electrically conductive local contact extends through each of the second insulator layer, etch stop layer and, first insulator layer to contact the at least one semiconductor device. The interconnect structure further includes at least one first layer contact element disposed on the etch stop layer and against the at least one conductive local contact.

Interconnect structure including middle of line (MOL) metal layer local interconnect on ETCH stop layer

Interconnect structure including middle of line (MOL) metal layer local interconnect on etch stop layer

The present application relates to an optical planarizing layer etch process. Embodiments include forming fins separated by a dielectric layer; forming a recess in the dielectric layer on each side of each fin, each recess being for a metal gate; forming sidewall spacers on each side of each recess; depositing a high-k dielectric liner in each recess and on a top surface of each of the fins; depositing a metal liner over the high-k dielectric layer; depositing a non-conformal organic layer (NCOL) over a top surface of the dielectric layer to pinch-off a top of each recess; depositing an OPL and ARC over the NCOL; etching the OPL, ARC and NCOL over a portion of the dielectric layer and recesses in a first region; and etching the portion of the recesses to remove residual NCOL present at a bottom of each recess of the portion of the recesses.

Block level patterning process

Methods of fabricating circuit structures including FinFET structures are provided, including: providing a substrate and a first material having a first threshold voltage above the substrate, and a second material having a second threshold voltage lower than the first threshold voltage above the first material; forming fins having base fin portions formed from the first material and upper fin portions formed from the second material; providing gate structures over the fins to form one or more FinFET structures, wherein the gate structures wrap around at least the upper fin portions and have an operating voltage lower than the first threshold voltage and higher than the second threshold voltage, so that the upper fin portions define a channel size of the one or more FinFET structures. Circuit structures including FinFET structures are also provided, in which the FinFET structures have a uniform channel size defined only by upper fin portions thereof.

FinFET structures having uniform channel size and methods of fabrication

Methods of fabricating fin structures having exposed upper fin portions with a uniform exposure height are disclosed herein. The fabrication methods include providing a substrate with plurality of fins and a dielectric material disposed between and over the plurality of fins, planarizing the dielectric material and the plurality of fins, and uniformly recessing the dielectric material to a pre-selected depth below upper surfaces of the plurality of fins to expose upper fin portions. The exposed upper fin portions, as a result of uniformly recessing the dielectric material, have a uniform exposure height above the recessed dielectric material. A protective film may be provided over the recessed dielectric material and exposed upper fin portions to preserve the uniform exposure height of the upper fin portions. The uniform exposure height of the exposed upper fin portions facilitates subsequent formation of one or more circuit structures above the substrate.

Methods of fabricating fin structures of uniform height

Methods of forming a dielectric layer on a substrate are described, and may include introducing a first precursor into a remote plasma region fluidly coupled with a substrate processing region of a substrate processing chamber A plasma may be formed in the remote plasma region to produce plasma effluents. The plasma effluents may be directed into the substrate processing region. A silicon-containing precursor may be introduced into the substrate processing region, and the silicon-containing precursor may include at least one silicon-silicon bond. The plasma effluents and silicon-containing precursor may be reacted in the processing region to form a silicon-based dielectric layer that is initially flowable when formed on the substrate.

Low shrinkage dielectric films

Methods of reducing dislocation in a semiconductor substrate between asymmetrical trenches are described. The methods may include etching a plurality of trenches on a semiconductor substrate and may include two adjacent trenches of unequal width separated by an unetched portion of the substrate. The methods may include forming a layer of dielectric material on the substrate. The dielectric material may form a layer in the trenches located adjacent to each other of substantially equivalent height on both sides of the unetched portion of the substrate separating the two trenches. The methods may include densifying the layer of dielectric material so that the densified dielectric within the two trenches of unequal width exerts a substantially similar stress on the unetched portion of the substrate that separates them.

Methods of reducing substrate dislocation during gapfill processing

A method of forming a silicon oxide layer is described. The method may include the steps of mixing a carbon-free silicon-containing precursor with a radical-nitrogen-and/or-hydrogen precursor, and depositing a silicon-nitrogen-and-hydrogen-containing layer on a substrate. The conversion of the silicon-nitrogen-and-hydrogen-containing layer to a silicon-and-oxygen-containing layer is then initiated by a low temperature anneal (a 'cure') in an ozone-containing atmosphere. The conversion of the silicon-and-nitrogen film to silicon oxide in the ozone-containing atmosphere may be incomplete and augmented by a higher temperature anneal in an oxygen-containing environment.

Methods of curing non-carbon flowable CVD films

A method of forming a silicon oxide layer is described. The method first deposits a silicon-nitrogen-and-hydrogen-containing (polysilazane) film by radical-component chemical vapor deposition (CVD). The polysilazane film is converted to silicon oxide by exposing the polysilazane film to humidity at low substrate temperature. The polysilazane film may also be dipped in a liquid having both oxygen and hydrogen, such as water, hydrogen peroxide and or ammonium hydroxide. These conversion techniques may be used separately or in a sequential combination. Conversion techniques described herein hasten conversion, produce manufacturing-worthy films and remove the requirement of a high temperature oxidation treatment. An ozone treatment may precede the conversion technique(s).

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Watervliet, NY, United States of America

Sukwon Hong