Micron Technology Incorporated

Intel Corporation

Other

Applied Materials, Inc.

Sujit Sharan

Gurtej S Sandhu

Dae-Woo Kim

Kirk D Prall

Howard E Rhodes

Jianyong Xie

Aleksandar Aleksov

Anand Srinivasan

Trung Tri Doan

Henning Braunisch

Philip J Ireland

Ravi T Iyer

Johanna M Swan

Ravindranath Vithal Mahajan

Andrew Paul Collins

Chia-Pin Chiu

Stefanie M Lotz

Debendra Mallik

Pai-Hung Pan

Ammar Derraa

Sairam Agraharam

Jeffrey W Honeycutt

Allen P Mardian

Paul F Smith

Paul Castrovillo

Hinmeng Au

Mei Yin Chang

Kemal Aygun

Digvijay Ashokkumar Raorane

Arnab Sarkar

Thomas Arthur Figura

Craig M Carpenter

Philip H Campbell

Martin Ceredig Roberts

Weimin Li

Zhiguo Qian

Neal R Rueger

Ceredig Roberts

Sukesh Sandhu

Yidnekachew S Mekonnen

Ajay Jain

Neha M Patel

Shankar Ganapathysubramanian

Vladimir Noveski

Gurtel Sandhu

Varatharajan Nagabushnam

Tim Johnson

Tim O'Brien

Rodrick J Hendricks

P J Ireland

Terry L Gilton

Robert L Sankman

Stefan Rusu

Donald S Gardner

Zhichao Zhang

Lyle D Breiner

Hugh E Stroupe

Chris W Hill

Ankur Agrawal

Carlton E Hanna

Vasudeva Atluri

Dongming He

Arghya Sain

Randy W Mercil

Lijiang Wang

Srinivas S Moola

Vijay Govindarajan

Matthew Escobido

Feras Eid

Guy T Blalock

Kristof Darmawikarta

Omkar G Karhade

Nitin A Deshpande

Wilfred Gomes

Tin Poay Chuah

Ashay A Dani

Howe Yin Loo

Xiaoqian Li

Xiaohong Jiang

Gudbjorg H Oskarsdottir

Ananth Prabhakumar

Chris Matayabas

Chris Rumer

Beverly J Canham

Yuxia Sun

Prashant D Parmar

Thomas J Debonis

Huang-Ta Chen

Biancun Xie

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly including a substrate having a conductive plane; and a bridge having first contacts at a first surface and second contacts at an opposing second surface, wherein the bridge is embedded in the substrate and coupled to the conductive plane in the substrate via the first contacts, wherein the bridge is coupled to a first die and a second die via the second contacts, and wherein the bridge does not include a silicon substrate.

Substrateless double-sided embedded multi-die interconnect bridge

Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having a lower insulating layer disposed thereon. The substrate has a perimeter. A metallization structure is disposed on the lower insulating layer. The metallization structure includes conductive routing disposed in a dielectric material stack. First and second pluralities of conductive pads are disposed in a plane above the metallization structure. Conductive routing of the metallization structure electrically connects the first plurality of conductive pads with the second plurality of conductive pads. An upper insulating layer is disposed on the first and second pluralities of conductive pads. The upper insulating layer has a perimeter substantially the same as the perimeter of the substrate.

Alternative surfaces for conductive pad layers of silicon bridges for semiconductor packages

Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, the electronic package comprises a base substrate. The base substrate may have a plurality of through substrate vias. In an embodiment, a first die is over the base substrate. In an embodiment a first cavity is disposed into the base substrate. In an embodiment, the first cavity is at least partially within a footprint of the first die. In an embodiment, a first component is in the first cavity.

Nested architectures for enhanced heterogeneous integration

Embodiments disclosed herein include electronic packages with a bridge that comprise improved power delivery architectures. In an embodiment, a bridge comprises a substrate and a routing stack over the substrate. In an embodiment, the routing stack comprises first routing layers, where individual ones of the first routing layers have a first thickness, and a second routing layer, where the second routing layer has a second thickness that is greater than the first thickness.

EMIB architecture with dedicated metal layers for improving power delivery

Metal-free frame designs for silicon bridges for semiconductor packages and the resulting silicon bridges and semiconductor packages are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon, the substrate having a perimeter. A metallization structure is disposed on the insulating layer, the metallization structure including conductive routing disposed in a dielectric material stack. A first metal guard ring is disposed in the dielectric material stack and surrounds the conductive routing. A second metal guard ring is disposed in the dielectric material stack and surrounds the first metal guard ring. A metal-free region of the dielectric material stack surrounds the second metal guard ring. The metal-free region is disposed adjacent to the second metal guard ring and adjacent to the perimeter of the substrate.

Metal-free frame design for silicon bridges for semiconductor packages

Guard ring designs enabling in-line testing of silicon bridges for semiconductor packages, and the resulting silicon bridges and semiconductor packages, are described. In an example, a semiconductor structure includes a substrate having an insulating layer disposed thereon. A metallization structure is disposed on the insulating layer. The metallization structure incudes conductive routing disposed in a dielectric material stack. The semiconductor structure also includes a first metal guard ring disposed in the dielectric material stack and surrounding the conductive routing. The first metal guard ring includes a plurality of individual guard ring segments. The semiconductor structure also includes a second metal guard ring disposed in the dielectric material stack and surrounding the first metal guard ring. Electrical testing features are disposed in the dielectric material stack, between the first metal guard ring and the second metal guard ring.

Guard ring design enabling in-line testing of silicon bridges for semiconductor packages

A multi-chip package includes a substrate () having a first side (), an opposing second side (), and a third side () that extends from the first side to the second side, a first die () attached to the first side of the substrate and a second die () attached to the first side of the substrate, and a bridge () adjacent to the third side of the substrate and attached to the first die and to the second die. No portion of the substrate is underneath the bridge. The bridge creates a connection between the first die and the second die. Alternatively, the bridge may be disposed in a cavity () in the substrate or between the substrate and a die layer (). The bridge may constitute an active die and may be attached to the substrate using wirebonds ().

Multi-chip package and method of providing die-to-die interconnects in same

Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first trace embedded in a package substrate. In an embodiment, the first trace comprises a first region, where the first region has a first width, and a second region, where the second region has a second width that is smaller than the first width.

Package design scheme for enabling high-speed low-loss signaling and mitigation of manufacturing risk and cost

A package substrate is disclosed. The package substrate includes a die package in the package substrate located at least partially underneath a location of a power delivery interface in a die that is coupled to the surface of the package substrate. Connection terminals are accessible on a surface of the die package to provide connection to the die that is coupled to the surface of the package substrate. Metal-insulator-metal layers inside the die package are coupled to the connection terminals.

Capacitor die embedded in package substrate for providing capacitance to surface mounted die

A groove alignment structure comprises an etch stop material and a substrate over the etch stop material. A set of grooves is along a first direction in a top surface of the substrate, and adhesive material is in a bottom of the set of grooves. Optical fibers are in the set of grooves over the adhesive material and a portion of the optical fibers extends above the substrate. A set of polymer guides is along the first direction on the top surface of the substrate interleaved with the set of grooves.

Silicon groove architectures and manufacturing processes for passive alignment in a photonics die

Growing community of inventors

Chandler, AZ, United States of America

Sujit Sharan