Micron Technology Incorporated

Sujeet V Ayyapureddi

Donald M Morgan

Edmund Gieske

Vasu Seeram

Raghukiran Sreeramaneni

Scott Eugene Smith

Yang Lu

Ameen D Akel

Amitava Majumdar

Suryanarayana B Tatapudi

Cagdas Dirik

Markus H Geiger

Robert Michael Walker

Matthew Alan Prather

Manoj Sinha

Brandon Roth

Danilo Caraccio

Christopher K Morzano

Randall J Rooney

Elliott Clifford Cooper-Balis

Elliott C Cooper-balis

Brent Keeth

Dean D Gans

Jeffrey P Wright

Yuan He

Tamara Schmitz

Jongtae Kwak

Gary L Howe

Simon J Lovett

Yoshinori Fujiwara

Joshua E Alzheimer

Victor Wong

Christian N Mohr

Dennis G Montierth

William F Jones

Thanh K Mai

Niccolò Izzo

Mark K Hadrick

Brian J Ladner

C Omar Benitez

Myung Gyoo Won

Don Morgan

Randy Brian Drake

Nicolo Izzo

Niccolo Izzo

Jack Riley

Andrew F Laforge

Niccolo′ Izzo

Apparatuses, systems, and methods for single-pass access of ECC information, metadata information, or combinations thereof. The memory array includes a number of column planes and an extra column plane. A memory device may be set in an ×4 single-pass operational mode. In this mode, the memory may store data in a selected ones of the column planes, and metadata may be stored in the extra column plane. An error correction code circuit (ECC) may store parity bits associated with the data and metadata in non-selected ones of the column planes. In this manner, the data, metadata, and parity may be accessed as part of a single access of the memory array.

Apparatuses and methods for single-pass access of ECC information, metadata information or combinations thereof

Apparatuses, systems, and methods for managing storage and retrieval of metadata at a memory. A metadata column address generator, during a metadata access operation, is configured to decode a subset of less than all of the bits of the column address to determine a metadata column address and a metadata column plane address corresponding to a particular one of column planes of a memory array. A column decoder is configured to facilitate a double cycle access operation to write data to or retrieve data from the plurality of column planes based on the column address and to write metadata to or retrieve metadata from a particular column corresponding to the metadata column address of the particular one of the column planes corresponding to the column plane address.

Apparatuses, systems, and methods for managing metadata storage at a memory

Methods, systems, and devices for output timing for channel loopback of a memory device are described. For example, a memory device may be configured to receive a first signal indicative of a logic value in accordance with a rising edge of a first clock signal, and to output a second signal indicative of the logic value in accordance with a falling edge of a second clock signal. In various examples, the second clock signal may be generated by the memory device based on receiving the first clock signal from the host device, or the first clock signal and the second clock signal may be the same clock signal, which may be generated at the memory device based on a different clock signal received from the host device. In some examples, the timing of the second signal may be different than timing implemented for other signaling from the memory device.

Output timing for channel loopback of a memory device

Apparatuses, systems, and methods for an enhanced ECC mode. The memory array includes a number of data column planes and an extra column plane. When the memory device is set in an Enhanced ECC mode, data is stored in a subset of the data column planes, and an error correction code circuit (ECC) stores corresponding parity data in one of a column plane other than one of the subset of data column planes or the extra column plane. In this manner, memory may be capable of performing single error correction or single error correction with double error detection (SECDED) depending on the mode selected.

Apparatuses and methods for configurable ECC modes

Systems, methods, and apparatuses related to determining a number of access line contacts for an access line in a memory device are described. An apparatus includes a first data plane, a second data plane, and a sub-access line driver (SAD), all coupled to a local access line. A first portion of the local access line between the SAD and the first data plane includes a first number of access line contacts, a second portion of the local access line between the SAD and the second data plane includes a second number of access line contacts, and the first number of access line contacts are determined by data corresponding to a first function of the first data plane and the second number of access line contacts are determined by data corresponding to a second function of the data plane.

Access line contacts for an access line in a memory device

Apparatuses, systems, and methods for variable input error correction code (ECC) circuits. Different modes of a memory device may involve different numbers of bits of information (e.g., data and/or metadata) being accessed. An ECC input circuit receives the variable number of bits of information and provides a fixed number of input bits. An ECC engine uses the input bits to generate parity (during a write) or to locate errors (during a read). The number of input bits may be based on a number of inputs of the ECC engine. The ECC input circuit may generate filler bits to add to the bits of information to generate the input bits.

Apparatuses and methods for variable input ECC circuits

Per-row recent and/or baseline error information for word lines may be stored along the word lines in some examples. In some examples, baseline error information may be stored in a fuse array. In some examples, the baseline error information may be loaded from the fuse array to a memory array. In some examples, based on the recent and/or baseline error information, the memory device may provide a post-package repair recommendation.

Apparatuses, systems, and methods for storing error information and providing recommendations based on same

Apparatuses, systems, and methods for dynamically allocated aggressor detection. A memory may include an aggressor address storage structure which tracks access patterns to row addresses and their associated bank addresses. These may be used to determine if a row and bank address received as part of an access operation are an aggressor row and bank address. The aggressor row address may be used to generate a refresh address for a bank identified by the aggressor bank address. Since the aggressor storage structure tracks both row and bank addresses, its storage space may be dynamically allocated between banks based on access patterns to those banks.

Apparatuses and methods for dynamically allocated aggressor detection

An exemplary memory controller includes a refresh manager circuit configured to provide a refresh command to a memory system via a command and address bus to initiate a refresh operation at a bank of the memory system. In response to provision of the refresh command, the refresh manager circuit is further configured to issue a bank status command to the host to indicate that the bank of the memory system has switched to unavailable.

Apparatuses and methods to deprioritize traffic to unavailable memory banks

Methods, systems, and devices for techniques for four cycle access commands are described. A memory device may communicate access commands with a host device over a command-address (CA) channel associated with multiple data channels. The host device may transmit an access command that includes an operation code indicating a type of the access command, a first address of the memory device that is a first target of the access command, and a second address of the memory device that is a second target of the access command. The first address may be associated with a first data channel, and the second address may be associated with a second data channel. Accordingly, the memory device and the host device may communicate first data corresponding to the first address over the first data channel and second data corresponding to the second address over the second data channel.

Techniques for four cycle access commands

Apparatuses, systems, and methods for memory module data drives. A memory module includes a number of memory devices as well as module logic. Each memory device provides data by driving voltages along a data bus with a data bus driver of the memory device. An output driver, which is located on the module logic receives the voltages along the data bus and drives voltages of an external data terminal to output the data. The output driver may have a greater drive strength than the data bus driver.

Apparatuses, systems, and methods for memory module data drivers

Apparatuses, systems, and methods for module level error correction. Multiple memory devices a packaged together in a memory module. The module includes a module error correction code (ECC) circuit which pools information multiple memory devices on the module. In an example read operation, multiple memory devices each provide a codeword which includes data bits and parity bits. The codewords may include data bits provided along a data bus and parity bits provided along a parity bus. The ECC circuit pools the codewords and detects errors in the pooled codewords.

Apparatuses, systems, and methods for module level error correction

An apparatus can include a number of memory devices and a controller coupled to one or more of the number of memory devices. The controller can be configured to determine whether a quantity of row activations directed to a row of the memory devices exceeds a row hammer criterion. The controller can be configured to select, responsive to determining that the row hammer criterion is met, a row hammer mitigation response from a plurality of row hammer mitigation responses available for initiation. The controller can be configured to initiate the selected row hammer mitigation response.

Selectable row hammer mitigation

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Boise, ID, United States of America

Sujeet V Ayyapureddi