Yamaha Corporation

Rohm Co., Ltd.

Suguru Tabara

Hiroshi Nakaya

Satoshi Hibino

Hiroshi Naito

A method of manufacturing a semiconductor device comprises, in patterning of a conductive film having a grain boundary on a very thin dielectric film, a first etching step of carrying out anisotropic etching until most of the conductive film in a flat portion disappears, and a second etching step of increasing a selective ratio to the dielectric film to etch the conductive film in an unnecessary portion such that a thickness of the dielectric film provided under the grain boundary can be held to prevent oxidation species from reaching an interface with a substrate after the first etching step.

Method of manufacturing semiconductor device

After a wiring material layer ( ) which is made of WSi or the like is formed on an insulation film covering a semiconductor substrate ( ), a first antireflection coating film ( ) which is made of TiON or TiN and a second antireflection coating film ( ) which is made of an organic material are sequentially formed on the wiring material layer ( ). Resist patterns ( to ) are formed on the second antireflection coating film ( ) by photolithography. The dry etching of the second antireflection coating film ( ) is performed using the resist patterns ( to ) as masks, after which the dry etching of the first antireflection coating film ( ) is conducted using the resist patterns ( to ) and patterns ( to ) of the second antireflection coating film ( ) as masks. The dry etching of the wiring material layer ( ) is effected using the resist patterns ( to ), the patterns ( to ) of the second antireflection coating film ( ) and patterns ( to ) of the first antireflection coating film ( ) as masks. The resist patterns ( to ) and the patterns ( to ) of the second antireflection coating film ( ) are removed. Lamination layers, each including one of patterns of the wiring material layer ( ) and one of the patterns of the first antireflection coating film ( ), form wiring layers. The resist patterns ( to ) and the patterns of the second antireflection coating film ( ) may be removed after the etching of the first antireflection coating film ( ), and the wring material layer ( ) may be etched using the patterns of the first antireflection coating film ( ) as masks.

Wiring forming method

A method of manufacturing a semiconductor device includes: a step of forming a conductive layer on a semiconductor substrate, the conductive layer being made of aluminum or aluminum alloy; a step of forming a resist pattern on the conductive layer, the resist pattern having an opening pattern including a narrow space having a high aspect ratio and an open space having a low aspect ratio; a main etching step of dry-etching the conductive layer by using the resist mask as an etching mask, wherein the conductive layer is almost etched in the open space having the low aspect ratio and not fully etched in the narrow space having the high aspect ratio; and an over etching step of further dry-etching the conductive layer by using the resist mask as an etching mask and by using as etchant a mixed gas of HCl gas and at least one species of gas selected from the group consisting of He, Ar, Ne and H,. The proposed method provides a process of etching an aluminum containing conductive layer at high patterning precision and with high reliability while suppressing electron shading damages.

Semiconductor manufacture method with aluminum wiring layer patterning process

A conductive layer (Ti, TiN, TiON, TiW, or a laminate thereof) having an antireflection function is formed on a gate electrode layer. The conductive layer is patterned by using a resist mask which is then removed. By using the patterned conductive layer as a mask, the gate electrode layer is patterned. An interlevel insulating film such as silicon oxide is deposited on the patterned gate electrode. A conductive layer having an antireflection function and a resist layer are formed on the interlevel insulating film. The resist layer is pattered, and the conductive layer is patterned by using the patterned resist layer as a mask. The patterned resist layer is removed. By using the patterned conductive layer as a mask, the interlevel insulating film is selectively etched to form a contact hole. A main conductive layer such as Al and a conductive layer having an antireflection function are formed and similar patterning is repeated.

Manufacture of semiconductor device with fine patterns

An electrode material layer of a WSi.sub.2 /polysilicon lamination layer and a conductive material layer for antireflection made of TiN or TiON and containing the direction &lt;200&gt; are sequentially deposited on a gate insulating film. The conductive material layer is patterned through dry etching using a resist layer as a mask to leave a portion of the conductive material layer. The resist layer may be as thin as capable of patterning the conductive material layer. After the resist layer is removed, the electrode material layer is patterned through dry etching using the conductive material layer as a mask to leave a portion of the electrode material layer. A lamination of the left electrode material layer and conductive material layer is used as a gate electrode layer. A lamination of the resist layer and conductive material layer may be used as a mask.

Conductive layer forming method using etching mask with direction &lt;200&gt;

A method of manufacturing a semiconductor device includes the steps of: a) forming a wiring layer on a semiconductor substrate, the wiring layer being an Al or Al alloy layer, or a laminated wiring layer including an Al or Al alloy layer and a Ti or Ti alloy layer formed thereon; b) coating a resist layer on the wringing layer and patterning the resist layer to form a wiring resist pattern; c) patterning the wiring layer to form a wiring pattern 3 by using the wiring resist pattern as a mask; d) forming an interlayer insulating film 5 on the semiconductor substrate to cover the wiring pattern; e) coating a resist layer on the interlayer insulating film and patterning the resist layer to form a connection hole resist pattern 6; f) dry-etching the interlayer insulating film with an etching gas containing fluorine to form a connection hole reaching the wiring pattern 3, by using the connection hole resist pattern as a mask; g) after the step f), rinsing the semiconductor substrate in a liquid 10 made of a material selected from a group consisting of water, alcohol, pyridine, and combinations thereof; and h) after the step g), ashing the connection hole resist pattern 6.

A conductive layer (Ti, TiN, TiON, TiW, or a laminate thereof) having an antireflection function is formed on a gate electrode layer. The conductive layer is patterned by using a resist mask which is then removed. By using the patterened conductive layer as a mask, the gate electrode layer is patterned. An interlevel insulating film such as silicon oxide is deposited on the patterned gate electrode. A conductive layer having an antireflection function and a resist layer are formed on the interlevel insulating film. The resist layer is pattered, and the conductive layer is patterned by using the patterned resist layer as a mask. The patterned resist layer is removed. By using the patterned conductive layer as a mask, the interlevel insulating film is selectively etched to form a contact hole. A main conductive layer such as Al and a conductive layer having an antireflection function are formed and similar patterning is repeated.

Semiconductor device with multi-layer wiring

A resist pattern having a high-density pattern area and a low-density pattern area is formed on a layered MNOS capacitor structure composed of a Ti(O)N layer and a WSi.sub.2 layer formed on nitride/oxide insulating layer on a semiconductor substrate. After the etching of the layered structure in the low-density resist pattern area is finished, the layered structure is further processed with plasma of HBr only, a mixed gas of a halogen-containing gas and oxygen gas, or a fluorine-containing gas, for a desired period of time, to give electron shading damage. In this plasma processing, the Ti(O)N layer is etched little. The electron shading damage is measured through the change in the flat band voltage of the MNOS capacitor.

Measurement of electron shading damage

A wiring pattern forming method includes the step of: forming resist patterns on an aluminum or aluminum alloy conductive layer, the resist patterns including a low density pattern area and a high density pattern area; etching and removing a portion of a thickness of the conductive layer by an etching process presenting anti-microloading effect by using the resist patterns as an etching mask, and etching and removing another portion of the thickness of the conductive layer by an etching process presenting microloading effect by using the resist patterns as an etching mask. A method of forming an aluminum or aluminum alloy wiring pattern is provided which can maintain a high etching rate and reduce electron shading damage.

Method of forming wiring pattern

A wafer having an interlayer insulating film on a silicon substrate and an Al alloy layer on the interlayer insulating film coated with a resist pattern is introduced into an etching chamber where the Al alloy layer is selectively etched in etchant gas plasma. A main etching process is performed under the etching conditions of a high plasma density until the interlayer insulating film 12 is exposed, and a succeeding over etching process is performed under the etching conditions of a low plasma density. A dry etching method and system is provided which can suppress generation of an abnormal shape or notch of a wiring pattern etched in low pressure and high density plasma, without sacrificing etching selectivity and with productivity being maintained high.

Dry etching suppressing formation of notch

A method for manufacturing a semiconductor device having a conductive film formed overlying an insulating film overlying the surface of a semiconductor substrate, the conductive film being made, for example, of a material such as polysilicon, WSi.sub.2, Al and Al alloy, and the like. An antireflection film, made of silicon nitride, for example, is formed overlying the surface of the conductive film, the antireflection film reducing light scattering from the conductive film and having a lower etching rate than the etching rate of the conductive film. The antireflection film is patterned to provide a mask for etching the conductive film, and the conductive film is etched using the patterned antireflection film as a mask to form a gate electrode for an MOS transistor, for example. Source and drain regions, for the MOS transistor, for example, are formed in the semiconductor substrate, and an interlayer insulating film is formed overlying the insulating film overlying the semiconductor substrate, the gate electrode and the antireflection film mask remaining on the surface of the gate electrode. The interlayer insulating film is selectively etched to form a deep contact hole, piercing to the semiconductor substrate in the source region, for example, and a shallow contact hole, piercing to the gate electrode. The antirefiection film mask remaining on the surface of the gate electrode retards the etching of the shallow contact hole so that the etchings of the shallow contact hole and of the deep contact hole are completed substantially simultaneously.

Method of manufacturing a semiconductor device using antireflection

A method of measuring electron shading damage which includes the steps of: a) preparing a characteristic curve of a flat band voltage change relative to an amount of injected charges, by intentionally flowing current through a first capacitor; b) preparing a second capacitor similar to the first capacitor; c) making a sample by using the second capacitor by forming a lamination of an insulating layer having an opening over the second capacitor, a conductive antenna layer connected to the conductive layer through the opening in the insulating layer, and an insulating mask pattern on the conductive antenna layer, the insulating mask pattern including a looped opening which leaves a separated pattern on the second capacitor; d) performing a dry process of the sample to fully remove the conductive layer under the loop opening; e) measuring a flat band voltage of the second capacitor before and after the dry process and calculating a change in the flat band voltage; and f) estimating from the calculated flat band voltage change an amount of charges injected into the second capacitor during the dry process, by referring to the characteristic curve. The method can reduce manufacture costs of a sample and provide a sufficiently high precision.

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Hamamatsu, Japan

Suguru Tabara