Samsung Electronics Co., Ltd.

Sug-hun Hong

Sang-jin Hyun

Yu-Gyun Shin

Dong-ho Ahn

Jae-Yoon Yoo

Yu-gyun Shin

Si-Young Choi

Sang-Bom Kang

Bon-Young Koo

Chul-Sung Kim

Dong-Ho Ahn

Hong-bae Park

Moon-han Park

Ja-hum Ku

Ja-Hum Ku

Gab-Jin Nam

Taek-Soo Jeon

Hyung-seok Hong

Hag-ju Cho

Jeong-Do Ryu

Chul-Joon Choi

Chul-joon Choi

Hoon-joo Na

Chul-sung Kim

In-sang Jeom

A semiconductor device that has a dual gate having different work functions is simply formed by using a selective nitridation. A gate insulating layer is formed on a semiconductor substrate including a first region and a second region, on which devices having different threshold voltages are to be formed. A diffusion inhibiting material is selectively injected into the gate insulating layer in one of the first region and the second region. A diffusion layer is formed on the gate insulating layer. A work function controlling material is directly diffused from the diffusion layer to the gate insulating layer using a heat treatment, wherein the gate insulting layer is self-aligned capped with the selectively injected diffusion inhibiting material so that the work function controlling material is diffused into the other of the first region and the second region. The gate insulating layer is entirely exposed by removing the diffusion layer. A gate electrode layer is formed on the exposed gate insulating layer. A first gate and a second gate having different work functions are respectively formed in the first region and the second region by etching the gate electrode layer and the gate insulating layer.

Methods of forming semiconductor devices having gates with different work functions using selective injection of diffusion inhibiting materials

Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer.

Methods of forming devices including different gate insulating layers on PMOS/NMOS regions

A trench isolation method for a semiconductor device, wherein a capping layer formed of an insulating material fills a recess generated at a border edge between an active area and an inactive area. The border edge is defined by a trench filled with insulating material. Filling the recess suppresses defects of the semiconductor device. Reduction of the isolating ability, due to the formation of gate poly residue during the forming of a gate, is prevented. Reduction of the threshold voltage of a transistor, caused by electric field concentration due to the gate poly residue, is suppressed. An oxide layer is also provided which protects an nitride pad during a plasma process.

Trench isolation method with an epitaxially grown capping layer

Oxide layers, including gate oxide layers having different thicknesses, are formed, plasma nitridized, and oxidized in an oxygen atmosphere containing hydrogen at a high temperature. Electron trap sites and stress occurring during plasma nitridation may be removed during oxidation.

Methods of fabricating oxide layers by plasma nitridation and oxidation

A method of forming an oxide layer on a semiconductor substrate includes thermally oxidizing a surface of the substrate to form an oxide layer on the substrate, and then exposing the oxide layer to an ambient including predominantly oxygen radicals to thereby thicken the oxide layer. Related methods of fabricating a recessed gate transistor are also discussed.

Methods of forming an oxide layer in a transistor having a recessed gate

A semiconductor device having a trench isolation region including an anti-oxidative liner formed to be thin enough to minimize etch wastage caused by a wet etching solution according to a wet loading effect, and a trench isolation method of forming the same. The semiconductor device includes a silicon substrate and a trench isolation region formed in the silicon substrate. A silicon epitaxial growth layer contacts the silicon substrate at a bottom surface of the trench isolation region and fills the lower half of the trench isolation region. A first oxide layer has an L-shaped cross-section and extends from a sidewall of the trench isolation region to a portion of the bottom surface of the trench isolation region. An anti-oxidative liner has an L-shaped cross-section, and extends between the first oxide layer and the silicon epitaxial growth layer, with its inner surface contacting the silicon epitaxial growth layer. A second oxide layer fills the upper half of the trench isolation region on the silicon epitaxial growth layer.

Semiconductor device having trench isolation structure and method of forming same

A method of forming a T-shaped isolation layer, a method of forming an elevated salicide source/drain region using the same, and a semiconductor device having the T-shaped isolation layer are provided. In the method of forming the T-shaped isolation layer, an isolation layer having a narrow trench region in the lower portion thereof and a wide trench region in the upper portion thereof is formed on a semiconductor substrate. Also, in the method of forming the elevated salicide source/drain region, the method of forming the T-shaped isolation layer is used. In particular, conductive impurities can also be implanted into the lower portion of the wide trench region which constitutes the head of the T-shaped isolation layer and is extended to both sides from the upper end of the narrow trench region by controlling the depth of the wide trench region in an ion implantation step for forming the source/drain region.

Method of forming T-shaped isolation layer, method of forming elevated salicide source/drain region using the same, and semiconductor device having T-shaped isolation layer

Trench isolation method

A multilayer oxide film, including at least two oxide layers having differing stress characteristics, is used in a trench isolation method. Preferably, at least a first one of the oxide layers has tensile stress characteristics and at least a second one of the oxide layers has compressive stress characteristics. Thus, during densification, the overall stress can be reduced. The multilayer film is preferably formed by sequentially stacking first and second oxide films which have opposite stress characteristics. In one example, the first oxide film is a tetra-ethyl-orthosilicate (TEOS)-O.sub.3 based chemical vapor deposition (CVD) oxide film and the second oxide film is selected from the group consisting of TEOS-based plasma-enhanced CVD (PECVD) oxide film, an SiH.sub.4 based PECVD oxide film and a high density plasma (HDP) oxide film. In another embodiment, the first oxide film is an HDP oxide film and the second film is a TEOS-O.sub.3 based CVD oxide film. Accordingly, integrated circuits with reduced stress may be fabricated, thereby allowing increased performance of the integrated circuits.

Trench isolation methods utilizing composite oxide films

An isolation method for a highly-integrated semiconductor device includes growing an epitaxial layer on the entire surface of a semiconductor substrate including over a trench on which an oxide layer is formed, thereby leaving the inside of the trench empty. A portion of the epitaxial layer which is located over the trench is then oxidized to form an isolation region.

Isolation method for semiconductor device using selective epitaxial

A trench isolated integrated circuit includes at least one void in the trench at the trench corner. The trench comprises a trench wall, a trench floor and a trench corner between the trench wall and the trench floor. An insulating region is included in the trench, including on the trench floor and on the trench wall. The insulating region is spaced apart from the trench corner to define a void at the trench corner. The insulating region may also be spaced apart from a portion of the trench wall, to define a second void on the trench wall that is spaced apart from the void at the trench corner. The voids may reduce stresses cased by the thermal mismatch between the insulating region and the integrated circuit substrate, to thereby improve integrated circuit reliability and/or performance. Methods of forming trench isolated integrated circuits according to invention include the steps of forming a trench in an integrated circuit substrate. The trench comprises a trench wall, a trench floor and a trench corner between the trench wall and the trench floor. A first insulating layer is formed on the trench wall and on the trench floor. A second insulating layer is formed on the first insulating layer opposite the trench wall and spaced apart from the trench floor. The first insulating layer is isotropically etched using the second insulating layer as a mask to form a void in the first insulating layer between the second insulating layer and the trench corner. A third insulating layer is formed on the second insulating layer, opposite the first insulating layer.

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Suwon, South Korea

Sug-hun Hong