Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Microcomputer System, Ltd.

Other

Renesas Electronics Corporation

Hitachi Ulsi Systems Co., Ltd.

Sueo Kawai

Akihiro Yaguchi

Asao Nishimura

Makoto Kitano

Kunihiro Tsubosaki

Gen Murakami

Junichi Saeki

Isamu Yoshida

Hiroshi Kikuchi

Kunihiko Nishi

Takashi Yokoyama

Akio Hasebe

Hiroshi Hozoji

Takashi Yamazaki

Kazuyoshi Oshima

Masahiro Ichitani

Aizo Kaneda

Shozo Nakamura

Hiroyoshi Kokaku

Noriyuki Kinjo

Masatsugu Ogata

Masanori Segawa

Syuuji Eguchi

Ichiro Anjo

Tetsuro Matsumoto

Ichiro Anjoh

Tetsurou Matsumoto

Hideo Miura

Ichio Shimizu

Hiromichi Suzuki

Kazunari Suzuki

Takahiro Naito

Ryuji Kohno

Yoshinori Miyaki

Toshio Hattori

Masachika Masuda

Yujiro Kajihara

Chikako Kitabayashi

Hiroyuki Ohta

Takahiro Daikoku

Nobuo Owada

Norio Ishitsuka

Naoya Kanda

Shigeki Hirasawa

Shigeharu Tsunoda

Ritsuro Orihashi

Kunio Matsumoto

Tadasi Sonobe

Tadashi Sonobe

Nae Yoneda

Michifumi Kawai

Hideo Yamakura

Michifumi Takeichi

Ikuo Kawaguchi

Masato Okazaki

Keiji Ohmura

Saburo Usami

Kazuo Yamazaki

Ichiro Miyano

Akio Hoshi

Naozumi Hatada

Toshihiro Yasuhara

Fumio Suzuki

Hiroshi Aoyama

Toshio Hatsuda

Shigeru Sakamoto

Toshinori Ozaki

Tosuke Hirata

Yumiko Seki

Tooru Yoshida

Yoshimasa Murakami

Souji Sakata

Toshio Ishizuki

Mitsuhiro Nitobe

Shinzi Saruwatari

In order to improve the package body cracking resistance of an LSI package at the reflow soldering and to provide both a leadframe suitable for fabricating the LSI package according to the flexible manufacturing system and an LSI using the leadframe, the adhered area between a semiconductor chipand a resin is enlarged by making the external size of a die padsmaller than that of the semiconductor chip to be mounted thereon. Moreover, a variety of semiconductor chipshaving different external sizes can be mounted on the die padby cutting the leading ends of leadsto a suitable length in accordance with the external sizes of the semiconductor chips

Leadframe semiconductor integrated circuit device using the same, and method of and process for fabricating the two

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the 'Lead-On-Chip' or 'Chip-On-Lead' structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Semiconductor device

As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the &ldquo;Lead-On-Chip&rdquo; or &ldquo;Chip-On-Lead&rdquo; structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Semiconductor device including a resin sealing member which exposes the

Semiconductor device having all outer leads extending from one side of a

Semiconductor device chip on lead and lead on chip manufacturing

Growing community of inventors

Iwama-machi, Japan

Sueo Kawai