International Business Machines Corporation

Jds Uniphase Corporation

Sudipta Kumar Ray

Mario John Interrante

Kathleen Ann Stalter

Peter Jeffrey Brofman

Raymond A Jackson

Shaji Farooq

John Ulrich Knickerbocker

William Edward Sablinski

Scott Ira Langenthal

Mukta S Farooq

Suresh D Kadakia

Mukta G Farooq

David Clifford Long

Benjamin V Fasano

Frank Louis Pompeo

Steven Paul Ostrander

Thomas Edward Lombardi

Mitchell S Cohen

Herbert I Stoller

Birendra N Agarwala

Harvey Charles Hamel

Mark G Courtney

Jason Lee Frankel

Gordon J Robbins

Robert Charles Dockerty

Ciro Neal Ramirez

Nicholas G Koopman

Gregory Blair Martin

Stephen Anthony DeLaurentis

Ronald Maurice Fraga

Sampath Purushothaman

Minhua Lu

David L Questad

Eric D Perfecto

Thomas Anthony Wassick

James Gardner Ryan

Richard Stephen Graf

Subhash Laxman Shinde

Kamalesh K Srivastava

William K Hogan

Erick G Walton

Amit Kumar Sarkhel

Paul A Totta

Arthur Bross

Dudley A Chance

Karl J Puttlitz, Sr

Raj N Master

Umar M Ahmad

David Justin West

Joseph M Harvilchuck

Aziz M Ahsan

Adolf E Wirsing

Joseph G Schaefer

Li-Chung Lee

Edward F Handford

Mark F Chadurjian

Eric D Pefecto

Peter Alfred Gruber

Hilton T Toy

Chandrasekhar Narayan

Steven Alan Cordes

Kwong Hon Wong

James L Speidell

How Tzu Lin

Wiren Dale Becker

Lester W Herron

David Peter Gaio

Sarah Huffsmith Knickerbocker

S Jay Chey

Lewis Sigmund Goldmann

Chandrika Prasad

Harsaran S Bhatia

Thomas J Fleischman

Jeannine Madelyn Trewhella

Anson Jay Call

Robert Anthony Rita

Shashi D Malaviya

Glenn Graham Daves

Patrick Anthony Coico

Dinesh Gupta

Daniel George Berger

Ananda H Kumar

Brenda Lee Peterson

James H Covell

Keshav B Prasad

Mark Harrison McLeod

Kathleen M Wiley

Chung W Ho

Paul A Zucco

Scott R Dwyer

L Wynn Herron

Susan J LaMaire

Somnath Bhattacharya

Robert K Lewis

Alan Platt

Shaji Faroon

Shaji Faroog

Keith F Beckman

Alice H Cooper-Joselow

Ananda Kumar

An electrically insulating substrate is provided. The electrically insulating substrate includes a set of areas to be formed into a set of printed circuit boards. Each of the set of areas is separated from others of the set of areas by a dicing channel. A set of signal wiring conductors is fabricated onto the set of areas of the electrically insulating substrate so that at least one of the set of signal wiring conductors terminates proximate to the dicing channel. A set of plated through holes is fabricated through at least one of the set of areas such that at least one of the set of plated through holes connects to at least one of the set of signal wiring conductors. The electrically insulating substrate is singulated along a set of singulation lines to form the set of printed circuit boards. The singulation lines intersect with the plated through holes, so that a portion of the plated through holes is exposed along the peripheral edge of the resulting printed circuit boards.

Method of fabricating printed circuit boards

An apparatus, system, and method are disclosed for connecting integrated circuit devices. A plurality of primary electrically conductive contacts and a plurality of primary electrically conductive pillars are electrically coupled to a primary integrated circuit device. The plurality of primary electrically conductive contacts form a pattern corresponding to secondary electrically conductive contacts disposed on one or more secondary integrated circuit devices. The plurality of primary electrically conductive pillars extends away from the primary integrated circuit device. The plurality of primary electrically conductive pillars forms a pattern that corresponds to substrate electrically conductive contacts that are disposed on a substrate. The plurality of primary electrically conductive pillars and associated connecting material provide a standoff height between the primary integrated circuit device and the substrate that is greater than or equal to a height of the one or more secondary integrated circuit devices.

Three dimensional stacked package structure

An electrical conductor is connected to a first microcircuit element having a first connector site axis and a second microcircuit having a second connector site axis. The first microcircuit and the second microcircuit are separated by and operatively associated with a first electrical insulator layer. The conductor and the first microcircuit element are separated by and operatively associated with a second electrical insulator layer. At least one of the first electrical insulator layer and the second electrical insulator layer comprise a polymeric material. The microcircuit includes a UBM and solder connection to a FBEOL via opening. Sufficiently separating the first connector site axis and the second connector site axis so they are not concentric, decouples the UBM and solder connection to the FBEOL via opening. This eliminates or minimizes electromigration and the white bump problems. A process comprises manufacturing the microcircuit.

Robust FBEOL and UBM structure of C4 interconnects

An apparatus, system, and method are disclosed for connecting an integrated circuit device to a substrate. A plurality of standard diameter pillars and three or more increased diameter pillars are disposed on an integrated circuit device. The increased diameter pillars have a diameter that is greater than the standard diameter pillars and a height that is similar to the standard diameter pillars. The standard diameter pillars and the increased diameter pillars form a pattern on the integrated circuit device that corresponds to contact pads on a substrate opposite the integrated circuit device. A first group of solder bumps is disposed between the standard diameter pillars and the contact pads. A second group of solder bumps is disposed between the increased diameter pillars and the contact pads. The second group of solder bumps has pre-connection heights that are greater than pre-connection heights of the first group of solder bumps.

Overcoming laminate warpage and misalignment in flip-chip packages

A microcircuit article of manufacture comprises an electrical conductor electrically connected to both a first microcircuit element at a site comprising a first connector site having a first connector site axis and a second microcircuit element at a site comprising a second connector site having a second connector site axis. The first microcircuit element and the second microcircuit element are separated by and operatively associated with a layer comprising a first electrical insulator, whereas the conductor and the first microcircuit element are separated by and operatively associated with a layer comprising a second electrical insulator. At least one of the first electrical insulator layer and the second electrical insulator layer comprise a polymeric electrical insulator. In another embodiment, both electrical insulator layers comprise polymeric insulator layers. The microcircuit includes a UBM and solder connection to a FBEOL via opening. Sufficiently separating the first connector site axis and the second connector site axis so they are not concentric decouples the UBM and solder connection to the FBEOL via opening to substantially eliminate or minimize inter alia, electromigration and the white bump problem typical of lead free solders employed in C4 systems. A process comprises manufacturing this type of microcircuit article.

A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier; one or more integrated circuit chips attached to a top surface of the chip carrier; a ceramic-based cap structure attached to the top surface of the chip carrier, and covering the one or more integrated circuit chips; and a conductive grid structure embedded within the chip carrier and the cap structure, the conductive grid structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction; wherein the conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

Structure for implementing secure multichip modules for encryption applications

A tamper resistant, integrated circuit (IC) module includes a ceramic-based chip carrier, one or more integrated circuit chips attached to the chip carrier, and a cap structure attached to the chip carrier, covering the one or more integrated circuit chips. A conductive grid structure is formed in the chip carrier and cap structure, the conductive structure having a plurality of meandering lines disposed in an x-direction, a y-direction, and a z-direction. The conductive grid structure is configured so as to detect an attempt to penetrate the IC module.

Method and structure for implementing secure multichip modules for encryption applications

A pre-thermal reflown dielectric interposer having a plurality of vias traversing through the interposer which correspond to the I/O pads on a chip and substrate. Cone shaped solder elements reside within the vias, whereby these solder elements are cone shaped prior to thermal reflow to permit a reduced force for allowing some non-planarity for joining the chip to the substrate. The interposer may comprise a polyester film, glass, alumina, polyimide, a heat curable polymer or an inorganic powder filler in an organic material. The interposer may also have an adhesive or adhesive layers disposed on the linear surfaces thereof. The present pre-thermal reflown interposer prohibits contact between the solder joints by isolating each of the joints and corresponding bonding pads, as well as preventing over compression of the solder joints by acting as a stand off.

Dielectric interposer for chip to substrate soldering

A process and apparatus for preparing an MCM for hat removal where the hat includes a piston thermally coupled to a corresponding chip. The apparatus includes a heater positioned to reflow a joint between the piston and a base of the hat; and a retractor for biasing the piston away from the corresponding chip. Implementation of the apparatus and process prevent a piston, as it moves across the top of a corresponding chip during mechanical shear to remove the hat, to impact chip(s) and surrounding components. In addition, since piston(s) are retracted, the likelihood of piston impact with or cracking of a chip is reduced. In addition, cutting into a corresponding chip having a tilted back surface is prevented. The need to replace chips and other electronic components when making other repairs may, therefore, be greatly reduced.

Preparing MCM hat for removal

A silicon based package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Forming via holes which extend through the UTSW, forming metallization in the via holes which extends through the UTSW, making electrical contact to the interconnection structure on the first surface. Then bond the metallization in the via holes to pads of a carrier.

Method of manufacture of silicon based package

An optical-electronic package for an electronic device provides electrical connections to the electronic device and optical fiber connections to the electronic device. The package includes a high thermal conductivity base which has a pedestal to support and provide heat transfer connection to the electronic device. A seal band is formed on the base and a casing is bonded to the seal band. The casing has side feedthroughs for the electrical connections from the electronic device, and the casing has top feedthroughs or grooves for the optical fiber connections from the electronic device. A lid is hermetically sealed to the top of the casing. The lid has retractable means for forming a bend in the optical fibers to provide strain relief when the lid is placed on the casing. The retractable means for forming a bend in the optical fibers is retractable once the lid is sealed on the casing.

Optoelectronic package structure and process for planar passive optical and optoelectronic devices

A method and structure for solderably coupling an electronic module (e.g. a ceramic or plastic ball grid array module) to a circuit board. A lead-free solder ball is soldered to the module without using a joining solder to effectuate the soldering. The solder ball comprises a tin-antimony alloy that includes about 3% to about 15% antimony by weight. The solder ball is soldered to the circuit board with a lead-free joiner solder. The joiner solder comprises a tin-silver-copper alloy that includes by weight about 95.5-96.0% tin, about 3.5-4.0% silver, and about 0.5-1.0% copper. The resultant solder connection between the module and the circuit board has a fatigue life of at least about 90% of a fatigue life of a reference structure. The reference structure has a 90Pb/10Sn solder ball joined to both the module and the circuit card by a 63Sn/37Pb joiner solder.

Lead-free solder structure and method for high fatigue life

A process and structure for forming an optical subassembly in an integrated circuit, comprising: defining electrically conducting lines and bonding pads in a metallization layer on a substrate; depositing a passivation layer over the metallization layer; etching the passivation layer to remove the passivation layer from each of the bonding pads and a portion of the metallization layer associated with each of the bonding pads; diffusing Cr from the lines proximate said bonding pads to prevent solder wetting down lines; bonding an optical device to one of the bonding pads; and attaching the substrate to a carrier utilizing solder bond attachment.

Method of preventing solder wetting in an optical device using diffusion of Cr

A multi chip module substrate arranged with repair vias and repair lines extending between repair vias of the chip sites of the module by which repairs can be effected to overcome defects in the module circuits and a method for effecting the repairs of defects in the circuits of this module. A defect can occur in any one of a first signal via, a second signal via, and a circuit line extending between and intended to electrically connect the first signal via and the second signal via. After a defective circuit is identified, the signal vias of the circuit are isolated. Then, the first signal via of the defective circuit is electrically connected to that repair via of the chip site having the first signal via that is connected to that repair via of the chip site having the second signal via and the second signal via of the defective circuit is electrically connected to that repair via of the chip site having the second signal via that is connected to that repair via of the chip site having the first signal via.

Apparatus and method for repairing electronic packages

Growing community of inventors

Wappingers Falls, NY, United States of America

Sudipta Kumar Ray